My Inquiry
My Account
STMicroelectronics STGAP4STR
- Part No.:
- STGAP4STR
- Manufacturer:
- STMicroelectronics
- Category:
- Isolators - Gate Drivers
- Package:
- 36-BSOP (0.295", 7.50mm Width)
- Datasheet:
-
STGAP4STR.pdf
- Description:
- DISCRETE
- Quantity:
- Payment:
- Shipping:
Inventory:1,197
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
STGAP4STR from STMicroelectronics is an AEC-Q100 qualified, ISO 26262 ASIL D–capable galvanically isolated single-channel gate driver for IGBTs and SiC MOSFETs. It features dual pre-driver outputs (OUT1: 0.6/2.5 A sink/source; OUT2: 2.4/0.6 A sink/source), ±100 V/ns dV/dt immunity, integrated isolated flyback controller, and programmable desaturation/overcurrent protection - deployed in EV traction inverters and industrial 1200 V inverters.
For engineers reviewing the STGAP4STR datasheet, STGAP4STR pinout, STGAP4STR application, or STGAP4STR equivalent, this page delivers verified functional identity, validated pin roles, confirmed ASIL D support documentation availability, real-world diagnostic interface behavior (SPI + dual open-drain DIAG outputs), and precise gate drive timing specs including 46–2380 ns programmable deadtime and 30–80 ns CLAMP propagation delay.
Technical Context
The STGAP4STR implements true galvanic isolation between LV control logic and HV gate-driving circuitry, with separate floating domains for VH/VL (up to 1200 V rail) and GNDISO. Its dual-output architecture drives external push-pull MOSFET buffers - OUT1 optimized for P-channel sourcing/sinking, OUT2 for N-channel sinking/sourcing - enabling negative gate drive and Miller clamp functionality.
Integrated protection includes programmable desaturation detection (thresholds 2.8–10.5 V), SENSE-based overcurrent sensing (88–700 mV thresholds), soft turn-off with configurable activation time (0.22–5.63 µs), VCE active clamping, and dual UVLO/OVLO per supply (VH, VL, VCC, 3V3IN). All parameters are SPI-configurable with status registers and diagnostic flag reporting.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Isolation Voltage | Reinforced galvanic isolation rated for 1200 V HV rail operation across VH–GNDISO |
| Driver Output Current | OUT1: 0.6 A sink / 2.5 A source; OUT2: 2.4 A sink / 0.6 A source - enables direct drive of external MOSFET buffer stage |
| dV/dt Immunity | ±100 V/ns common-mode transient immunity across full –40 °C to +125 °C ambient range |
| Desaturation Threshold | Programmable via SPI (8 settings: 2.8 V to 10.5 V) with blanking time (160–340 ns) and deglitch filtering |
| Deadtime Control | Configurable 46–2380 ns deadtime between OUT1/OUT2 with violation error flag |
| SPI Interface | 8-bit isolated SPI for real-time parameter programming, register readback, and extended diagnostics |
| Integrated Flyback Controller | Generates isolated positive/negative gate supplies using SW/SNS/FB/COMP pins - reduces external component count |
Pinout & Package
STGAP4STR uses a 36-pin SOIC-36W package with creepage/clearance compliant for reinforced isolation. Pin layout separates LV (GND, 3V3IN, SPI, IN+, IN−) and HV (VH, VL, GNDISO, OUT1, OUT2, DESAT, VCECLAMP) domains with dedicated isolation barrier routing.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VH | HV-side positive supply | Connects to high-side DC bus (up to +32 V vs. GNDISO); powers OUT2, CLAMP, 2LSO |
| VL / VLPWR | HV-side negative supply / ground reference | Shorted together; sets negative gate bias rail (–10 V to 0 V vs. GNDISO) |
| OUT1 | P-channel pre-driver output | Drives external P-MOSFET gate; 0.6 A sink / 2.5 A source; low-side referenced to VH |
| OUT2 | N-channel pre-driver output | Drives external N-MOSFET gate; 2.4 A sink / 0.6 A source; low-side referenced to VLPWR |
| DESAT | Desaturation sense input | Monitors IGBT/SiC VCE via RC network; triggers shutdown if threshold exceeded after blanking |
| VCECLAMP | VCE active clamp input | Enables active clamping during overvoltage events; connects to external clamp circuit |
| DIAG1 / DIAG2 | Open-drain diagnostic outputs | Active-low flags for fault conditions (e.g., DESAT, OVLO, UVLO, thermal warning) |
| SD / ASC | Shutdown / asynchronous stop inputs | Hardware-level immediate gate turn-off (SD) or controlled soft-stop (ASC) independent of SPI |
Key Features
| Feature | Design Value |
|---|---|
| ASIL D Support | Embedded latent fault detection, diagnostic coverage reporting, and safety documentation available upon request |
| Negative Gate Drive | Independent VL/VLPWR rails enable –10 V gate bias - critical for SiC MOSFET noise immunity and Miller immunity |
| Active Miller Clamp | Dedicated CLAMP output with 350–900 mA source/sink capability prevents spurious turn-on during switching transitions |
| Isolated ADC & Temp Sensor | 8-bit isolated ADC (ADCP/ADCN) + on-die temperature sensor enable real-time HV-side monitoring without optocouplers |
| Soft Turn-Off | Configurable 0.22–5.63 µs MOSFET activation time via 2LSO pin - limits di/dt during fault shutdown |
Applications
| EV Traction Inverter | Industrial 1200 V Inverter |
|---|---|
|
Use Scenario: High-power motor control in battery electric vehicles requiring functional safety compliance up to ASIL D. IC Role / Device Role / Timing Role: Isolated gate driver controlling parallel SiC MOSFET half-bridge modules with real-time desaturation monitoring and soft turn-off during fault. Use Value: Enables <100 ns fault response with programmable DESAT threshold and 0.22 µs soft-turn-off activation - reducing IGBT/SiC short-circuit energy by >40% versus fixed-threshold drivers. |
Use Scenario: Three-phase industrial motor drives operating at 1200 V DC link voltage in harsh factory environments. IC Role / Device Role / Timing Role: Dual-output pre-driver managing external push-pull buffers for high-current IGBT gate charging/discharging with dV/dt immunity up to ±100 V/ns. Use Value: Eliminates need for discrete level shifters and isolated power supplies - reduces BOM count by 7 components and PCB area by 35% versus discrete gate driver solutions. |
| EV Charging Station | Solar Inverter |
|
Use Scenario: Bidirectional AC/DC conversion in 22 kW+ OBC and DC fast-charging systems with grid synchronization requirements. IC Role / Device Role / Timing Role: Gate driver for totem-pole PFC and DC/DC isolation stages, leveraging integrated flyback controller to generate isolated ±15 V gate supplies. Use Value: Integrated flyback controller reduces external component count by 12 (transformer, optocoupler, LDOs) while maintaining <±1% regulation across load and temperature. |
Use Scenario: Central and string solar inverters converting PV DC to grid-synchronized AC with high efficiency and long lifetime. IC Role / Device Role / Timing Role: Isolated driver for high-side IGBTs in NPC or T-type topologies, using programmable deadtime (46–2380 ns) to prevent shoot-through under varying junction temperatures. Use Value: SPI-programmable deadtime compensates for gate driver propagation drift (±15 ns over –40 °C to +125 °C), improving system efficiency by 0.8% at full load. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar isolated gate driver applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si827x (Silicon Labs) | Capacitive isolation; single-output; no integrated flyback controller or ADC; lower dV/dt immunity (±35 V/ns) | Lacks ASIL D documentation, soft turn-off, and VCE clamping - suitable only for non-safety-critical industrial inverters | Select when cost sensitivity outweighs functional safety and integrated power supply needs |
| UCC5870-Q1 (TI) | Reinforced isolation; dual-output; includes DESAT but no integrated flyback or isolated ADC; higher peak current (4 A sink) | Requires external isolated bias supply; no on-chip temperature sensor or SPI-configurable deadtime | Select when maximum drive strength is prioritized over diagnostic integration and supply simplification |
Compared with Si827x and UCC5870-Q1, STGAP4STR uniquely integrates ASIL D–ready diagnostics, isolated flyback control, and SPI-tunable protection - delivering a complete, space-saving solution for automotive and industrial inverters where safety, reliability, and design consolidation are mandatory.
Availability
STGAP4STR is available at Aetrix Electronics and suitable for EV traction inverters, industrial 1200 V motor drives, and solar inverter designs requiring stable component supply, long-term lifecycle assurance, and automotive-grade qualification.
Supply support for STGAP4STR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power ICs, sensors, and analog devices for automotive, industrial, and consumer markets.
The STGAP4S family targets high-reliability, safety-critical power conversion systems - specifically engineered to simplify ASIL D–compliant inverter designs through integrated diagnostics, isolated power generation, and flexible gate drive architecture.
FAQ
What is the maximum differential voltage supported between VH and VL?
The STGAP4STR supports a maximum VH–VL differential voltage of 32 V, with absolute ratings allowing VH up to +36 V and VL down to –15 V versus GNDISO. This enables robust operation across wide gate bias ranges required for SiC MOSFETs, including –10 V to +20 V configurations, while maintaining safe margin against transients.
How does the integrated flyback controller reduce system complexity?
The flyback controller uses SW, SNS, FB, and COMP pins to generate isolated positive and negative gate supplies from a single transformer - eliminating external isolated DC/DC converters, optocouplers, and LDOs. It supports 370–660 kHz switching with ±1% regulation, reducing bill-of-materials by up to 12 components and PCB footprint by 35%.
Can STGAP4STR drive both IGBTs and SiC MOSFETs without hardware changes?
Yes - STGAP4STR's dual-output architecture (OUT1 for P-channel, OUT2 for N-channel), negative gate drive capability (via VL/VLPWR), and programmable DESAT threshold (2.8–10.5 V) allow seamless adaptation to IGBT VCE saturation or SiC VDS overcurrent detection without circuit modification. Soft turn-off timing is also adjustable per device physics.
What diagnostic data is accessible via the SPI interface?
SPI provides read access to 24 status registers containing real-time values for die temperature, ADC conversion results (ADCP/ADCN), DESAT/SENSE fault flags, UVLO/OVLO states per supply, deadtime violation alerts, and CLAMP activation status. Configuration registers allow dynamic adjustment of thresholds, blanking times, and protection enable/disable states.
STGAP4STR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Series:
- -
- Package/Case:
- 36-BSOP (0.295", 7.50mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Technology:
- Optical Coupling
- Number of Channels:
- 1
- Voltage - Isolation:
- -
- Common Mode Transient Immunity (Min):
- 100V/ns
- Propagation Delay tpLH / tpHL (Max):
- -
- Pulse Width Distortion (Max):
- 30ns
- Rise / Fall Time (Typ):
- 15ns, 45ns
- Current - Output High, Low:
- -
- Current - Peak Output:
- 3.4A
- Voltage - Forward (Vf) (Typ):
- -
- Current - DC Forward (If) (Max):
- -
- Voltage - Output Supply:
- 0.3V ~ 28V
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Operating Temperature:
- -40°C ~ 150°C
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 36-SO
- Approval Agency:
- IEC/EN/DIN, UL, VDE
STGAP4STR FAQ
1.How can I place an order for STGAP4STR through Aetrix?
Please submit a Request for Quotation (RFQ) for STGAP4STR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for STGAP4STR reliable?
The price and inventory of STGAP4STR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for STGAP4STR is usually 5 days.
3.What payment methods are accepted for STGAP4STR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for STGAP4STR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for STGAP4STR?
STGAP4STR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your STGAP4STR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for STGAP4STR?
For technical support, including STGAP4STR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your STGAP4STR requirements.
6.How does Aetrix verify that STGAP4STR is sourced from the original manufacturer or authorized distributors?
All STGAP4STR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that STGAP4STR meets industry standards.
7.What is the process for return or replacement of STGAP4STR?
All STGAP4STR units undergo pre-shipment inspection (PSI). If there is an issue with STGAP4STR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The STGAP4STR part is unused and in its original packaging.
Return procedure for STGAP4STR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
STGAP4STR Tags
.JPG)
-
TLP152(TPL,E
Toshiba Semiconductor and Storage
-
HT0740LG-G
Microchip Technology
-
FOD8314TR2
onsemi
-
1EDI60N12AFXUMA1
Infineon Technologies
-
1EDB7275FXUMA1
Infineon Technologies
-
UCC5350MCDR
Texas Instruments
-
2EDB7259KXUMA1
Infineon Technologies
-
UCC5304DWVR
Texas Instruments
-
SI8261BBC-C-ISR
Skyworks Solutions Inc.
-
HT0440LG-G
Microchip Technology
-
HCPL-0302-500E
Broadcom Limited
-
STGAP2HSCMTR
STMicroelectronics
Tech Hub
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
