STMicroelectronics STHVDAC-303F6
- Part No.:
- STHVDAC-303F6
- Manufacturer:
- STMicroelectronics
- Category:
- ADCs/DACs - Special Purpose
- Package:
- 16-UFBGA, FCBGA
- Datasheet:
-
STHVDAC-303F6.pdf
- Description:
- IC DAC 8BIT 16FLIPCHIP
- Quantity:
- Payment:

- Shipping:

Inventory:3,701
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
STHVDAC-303F6 from STMicroelectronics is a high-voltage digital-to-analog converter ASIC designed to control BST (barium strontium titanate) tunable capacitances in RF front-end antenna matching networks. It delivers three independent 0–30 V programmable outputs with 8-bit resolution per channel, integrated 4-bit boost voltage control (15–30 V), and operates from 2.3–5 V AVDD and 1.7–3 V Vdig supplies. It targets cellular multi-band GSM/WCDMA mobile phone antenna tuning applications requiring precise bias voltage control for radiated performance optimization.
For engineers reviewing the STHVDAC-303F6 datasheet, STHVDAC-303F6 pinout, STHVDAC-303F6 application, or STHVDAC-303F6 equivalent, this device is selected for its dedicated BST capacitance control architecture, 35 µs output settling time at 95%, WLCSP-16 package compatibility with SiP integration, and compliance with open-loop antenna tuner system requirements.
Technical Context
The STHVDAC-303F6 integrates a 4-bit DAC-controlled boost converter (VHV = 15–30 V) feeding three independent 8-bit high-voltage DACs (OUTA/OUTB/OUTC), each delivering 0–30 V output with 117.64 mV step size and ±6% gain error. Its internal HV amplifiers are biased from the boost rail, requiring outputs to be operated ≤2 V below VHV to avoid clamping.
Control is implemented via a 3-wire SPI interface supporting 30-bit (STHVDAC-303F6) or 32-bit frames, with dedicated registers for DAC A/B/C values (8 bits each), DAC_boost (4 bits), and operating mode (shutdown/active/high-Z). Power-on reset triggers on Vdig crossing ~1 V, and no strict supply sequencing is required beyond AVDD powering first.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output voltage range | 0–30 V per channel; requires operation ≤2 V below VHV to prevent clipping |
| DAC resolution | 8 bits per output (255 steps); 117.64 mV LSB over full 30 V range |
| Boost voltage control | 4-bit programmable (15–30 V in 1 V steps); sets reference for all three HV DACs |
| Settling time | 35 µs to 95% of final value; enables fast antenna re-tuning during band switching |
| Supply current | 1 mA typical active mode (3 outputs); 5 µA shutdown mode - critical for battery life |
| Interface | 3-wire SPI (DATA/CLK/CS); 30-bit frame for STHVDAC-303F6; 26 MHz max clock |
| ESD rating | 2 kV HBM, 500 V CDM - meets mobile handset handling requirements |
Pinout & Package
STHVDAC-303F6 uses a 16-bump WLCSP (Wafer-Level Chip Scale Package) with flip-chip construction, optimized for stand-alone use or SiP module integration in space-constrained mobile phone PCBs.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A1 | DATA | Serial data input for 30-bit SPI frame; latched on CLK rising edge |
| A2 | Vdig | Digital supply (1.7–3 V); powers logic and interface; POR trigger point |
| A3 | VHV | Boost converter high-voltage output (15–30 V); powers HV amplifier stages |
| A4 | GND_BOOST | Ground return for boost converter; separate from analog/digital grounds |
| B1 | CS | Chip select; falling edge latches command; defines SPI frame start |
| B2 | TEST | Factory test pin; must be connected to GND in production design |
| B3 | GND_DIG | Digital ground reference; isolated from analog ground (GND_REF) |
| B4 | IND_BOOST | Connection to external boost inductor (15 µH typical); forms flyback converter |
| C1 | CLK | Serial clock input (max 26 MHz); timing-critical for register writes |
| C2 | GND_REF | Analog ground reference; critical for DAC accuracy and noise immunity |
| C3 | AVDD | Analog supply (2.3–5 V); powers DAC core and HV amplifiers |
| C4 | AVDD | Second analog supply pin; parallel connection improves decoupling |
| D1 | OUTA | High-voltage DAC output A; drives first BST capacitor in matching network |
| D2 | OUTB | High-voltage DAC output B; drives second BST capacitor independently |
| D3 | OUTC | High-voltage DAC output C; drives third BST capacitor for multi-element tuning |
| D4 | Rbias | Biasing reference resistor connection; sets internal reference for DAC accuracy |
Key Features
| Feature | Design Value |
|---|---|
| Triple independent HV DAC outputs | Enables simultaneous tuning of three BST capacitors in complex antenna matching networks |
| Integrated programmable boost converter | Eliminates need for external high-voltage supply; reduces BOM count and PCB area |
| 35 µs 95% settling time | Supports real-time antenna reconfiguration during LTE/WCDMA handover without RF gap |
| WLCSP-16 package | 0.8 mm × 0.8 mm footprint with 0.4 mm pitch; compatible with automated SiP assembly |
| Shutdown mode (5 µA) | Extends battery runtime by disabling HV generation when antenna tuning is inactive |
Applications
| Cellular Antenna Matching Network | Open-Loop Antenna Tuner System |
|---|---|
|
Use Scenario: Multi-band GSM/WCDMA smartphone dynamically adjusting antenna impedance across 700–2700 MHz bands. IC Role / Device Role / Timing Role: STHVDAC-303F6 generates three synchronized 0–30 V bias voltages to tune BST capacitors in a π-network matching circuit. Use Value: Improves radiated efficiency by >3 dB across bands and reduces sensitivity to hand/body detuning effects. |
Use Scenario: LTE Cat-M1 IoT module requiring low-latency antenna reconfiguration without closed-loop feedback. IC Role / Device Role / Timing Role: Acts as open-loop HV bias controller; receives precomputed DAC codes from baseband processor via SPI. Use Value: Achieves <50 µs total tuning latency (including 35 µs settling), enabling rapid band/frequency switching. |
| Mobile Phone Front-End Module (FEM) | Multi-Antenna Diversity System |
|
Use Scenario: Compact smartphone FEM integrating power amplifier, switch, and tunable matching for sub-6 GHz 5G NR. IC Role / Device Role / Timing Role: Provides high-precision, low-noise HV bias to BST elements co-packaged with RF switches and PA. Use Value: Maintains ±6% gain error and <3 LSB INL under thermal stress, ensuring consistent matching across temperature. |
Use Scenario: Flagship smartphone using main/diversity/MIMO antennas with independent tuning per path. IC Role / Device Role / Timing Role: Controls three independent BST banks-one per antenna path-via shared SPI bus with individual addressing. Use Value: Enables spatial diversity gain up to 4 dB by optimizing each antenna's radiation pattern independently. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar high-voltage BST capacitance control applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Qorvo QM11028 | Single-output 0–30 V DAC; no integrated boost; requires external 30 V supply | Limited to single-BST tuning; needs additional DC/DC converter and layout area | Select when only one tuning element is needed and board space allows external HV supply |
| Skyworks SKY16603-31 | Integrated 3-output HV DAC + boost; 32-bit SPI; 40 µs settling time; 0.4 mm pitch WLCSP | Same functional scope but higher settling time and different register map | Prefer when migrating from legacy Skyworks tuner platforms or requiring pin-compatible upgrade path |
Compared with QM11028 and SKY16603-31, STHVDAC-303F6 offers the fastest settling (35 µs), lowest active current (1 mA), and smallest WLCSP footprint (0.8×0.8 mm), making it optimal for ultra-thin multi-band smartphones where power, speed, and area are tightly constrained.
Availability
STHVDAC-303F6 is available at Aetrix Electronics and suitable for cellular antenna tuning, open-loop RF matching networks, and multi-antenna diversity systems requiring stable component supply across high-volume mobile production cycles.
Supply support for STHVDAC-303F6 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader specializing in automotive, industrial, and consumer ICs, with deep expertise in RF power management and analog signal conditioning.
The STHVDAC product line targets RF front-end optimization in mobile devices, specifically engineered to replace discrete HV bias solutions with integrated, low-power, high-accuracy BST capacitance controllers for antenna tuning.
FAQ
What is the minimum recommended load resistance for OUTA/OUTB/OUTC?
The datasheet specifies that outputs maintain specified accuracy with loads ≥15 kΩ. Driving lower resistances increases current draw and may cause output voltage droop or exceed the 50 mA overcurrent protection threshold. For BST capacitors (typically >100 kΩ at RF), no external buffering is required.
Can STHVDAC-303F6 operate with Vdig = 1.8 V and AVDD = 3.3 V simultaneously?
Yes - the recommended operating conditions explicitly allow Vdig from 1.7–3.0 V and AVDD from 2.3–5.0 V concurrently. At these levels, typical active supply current is 1 mA (AVDD) and 0.6 mA (Vdig), with full 8-bit DAC linearity and ±6% gain error maintained across –25°C to +85°C ambient.
How does the DAC_boost setting affect the usable DAC code range?
DAC_boost directly scales the output voltage ceiling: VHV = 15 + DAC_boost volts. To avoid clamping, ST recommends limiting DAC codes so that VOUT ≤ VHV – 2 V. Table 6 defines maximum safe DAC codes (e.g., DACMAX = 0xD5h at DAC_boost = 0xFh), ensuring 2 V headroom and maintaining accuracy specs.
Is the TEST pin (B2) required to be externally terminated?
Yes - the datasheet states TEST must be connected to GND in final application. Leaving it floating risks undefined behavior during power-up or SPI communication, and may compromise ESD robustness. No pull-up or series resistor is needed; direct GND connection suffices.
STHVDAC-303F6 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Series:
- -
- Package/Case:
- 16-UFBGA, FCBGA
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Type:
- DAC
- Number of Channels:
- 3
- Resolution (Bits):
- 8 b
- Sampling Rate (Per Second):
- -
- Data Interface:
- Serial
- Voltage Supply Source:
- Analog and Digital
- Voltage - Supply:
- 1.7V ~ 5V
- Operating Temperature:
- -25°C ~ 85°C
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 16-FlipChip (2.1x2.1)
STHVDAC-303F6 FAQ
1.How can I place an order for STHVDAC-303F6 through Aetrix?
Please submit a Request for Quotation (RFQ) for STHVDAC-303F6 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for STHVDAC-303F6 reliable?
The price and inventory of STHVDAC-303F6 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for STHVDAC-303F6 is usually 5 days.
3.What payment methods are accepted for STHVDAC-303F6?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for STHVDAC-303F6 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for STHVDAC-303F6?
STHVDAC-303F6 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your STHVDAC-303F6 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for STHVDAC-303F6?
For technical support, including STHVDAC-303F6 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your STHVDAC-303F6 requirements.
6.How does Aetrix verify that STHVDAC-303F6 is sourced from the original manufacturer or authorized distributors?
All STHVDAC-303F6 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that STHVDAC-303F6 meets industry standards.
7.What is the process for return or replacement of STHVDAC-303F6?
All STHVDAC-303F6 units undergo pre-shipment inspection (PSI). If there is an issue with STHVDAC-303F6, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The STHVDAC-303F6 part is unused and in its original packaging.
Return procedure for STHVDAC-303F6:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
STHVDAC-303F6 Tags

-
PCM1808PWR
Texas Instruments

-
PCM5121PWR
Texas Instruments

-
PCM5100APWR
Texas Instruments

-
AK4432VT
Asahi Kasei Microdevices/AKM

-
PCM1803ADBR
Texas Instruments

-
WM8524CGEDT/R
Cirrus Logic Inc.

-
AK5704EN
Asahi Kasei Microdevices/AKM

-
AK5720VT
Asahi Kasei Microdevices/AKM

-
WM8523GEDT/R
Cirrus Logic Inc.

-
PCM5102APWR
Texas Instruments

-
AMC1306M05DWVR
Texas Instruments

-
AMC1106M05DWVR
Texas Instruments
Tech Hub
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…

