STMicroelectronics STLVDS385BTR

Overview

STLVDS385BTR from STMicroelectronics is a 24-bit RGB + 4-control-line LVDS transmitter for flat-panel display interfaces, supporting 20–85 MHz clock rates, 297.5 MB/s bandwidth, and programmable rising/falling-edge strobe mode. It converts 28-bit LVCMOS/LVTTL data into four LVDS data streams plus one LVDS clock channel, targeting VGA/SVGA/XGA and single/dual-pixel SXGA LCD timing applications.

For engineers reviewing the STLVDS385BTR datasheet, STLVDS385BTR pinout, STLVDS385BTR application, or STLVDS385BTR equivalent, key selection criteria include differential output swing (345 mV typ), power-down current (<200 µA), set/hold timing (2.5 ns setup, 0 ns hold), and TSSOP56 package compatibility with high-density FPD-Link routing.

Technical Context

The STLVDS385BTR integrates a PLL with no external components and supports dual-strobe edge programming via R_FB pin, enabling interoperability with falling-edge receivers without logic translation. Its transmit architecture samples 28 bits per clock cycle and maps RGB/control signals across four 595 Mbps LVDS lanes plus a dedicated clock lane.

It delivers best-in-class set/hold times on TTL inputs and maintains <130 mW typical power at 85 MHz grayscale operation. Output jitter is specified at 110–150 ps cycle-to-cycle at 85 MHz, and LVDS outputs comply fully with TIA/EIA-644 standard voltage levels and noise immunity requirements.

Key Specifications

Pinout & Package

STLVDS385BTR is housed in a 56-pin TSSOP package (JEDEC MO-153, 14.0 × 7.5 mm body, 0.5 mm pitch) with dedicated power/ground segmentation for TTL inputs, PLL, and LVDS outputs to minimize crosstalk and supply noise coupling.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar LVDS transmitter applications.

Compared with SN65LVDS386 and NB3N3020B, STLVDS385BTR uniquely combines strobe-edge programmability, zero-external-component PLL, and full 28-bit control/data mapping - making it optimal for flexible, low-EMI, and thermally constrained flat-panel designs requiring interoperability across multiple GPU platforms.

Availability

STLVDS385BTR is available at Aetrix Electronics and suitable for desktop monitor interfaces, laptop LCD timing control, industrial HMI displays, and digital signage controllers requiring stable component supply and long-term lifecycle support.

Supply support for STLVDS385BTR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, specializing in automotive, industrial, and consumer ICs with strong analog and mixed-signal design heritage.

The STLVDS385 belongs to ST's Flat Panel Display Link transmitter product line, engineered specifically for low-EMI, high-reliability video interface solutions in space-constrained and thermally demanding display systems.

FAQ

What is the function of the R_FB pin on STLVDS385BTR?

The R_FB pin configures the transmitter's strobe edge polarity: tied to VCC for rising-edge sampling of TxCLKIN, or grounded/NC for falling-edge sampling. This enables direct interoperability with both rising- and falling-edge graphics controllers without external logic, and is validated in Figure 11 and Table 1 of the datasheet.

Does STLVDS385BTR require external components for PLL operation?

No. The STLVDS385BTR integrates a fully self-contained PLL that requires no external crystal, capacitors, or resistors. This is confirmed in the "DESCRIPTION" section and "PLL REQUIRES NO EXTERNAL COMPONENTS" bullet on page 1 of the datasheet, and verified by the absence of any PLL-related passive component footprints in the TSSOP56 mechanical drawing.

What display resolutions does STLVDS385BTR support at maximum clock frequency?

At 85 MHz, STLVDS385BTR supports single-pixel SXGA (1280×1024) and dual-pixel SXGA (1280×2048) with full RGB+control timing. It also supports VGA (640×480), SVGA (800×600), and XGA (1024×768) at lower clock rates down to 20 MHz, as explicitly stated in the "SUPPORTS VGA, SVGA, XGA AND SINGLE/DUAL PIXEL SXGA" specification.

How is power-down implemented and what is its effect on LVDS outputs?

Asserting PWRDWN low places all five LVDS outputs (four data + one clock) into high-impedance tri-state mode, reducing supply current to ≤200 µA. This behavior is documented in the PIN DESCRIPTION (pin 32), ELECTRICAL CHARACTERISTICS table (ICCTZ parameter), and Figure 10 (Transmitter Power Down Delay), ensuring safe hot-plug and low-power standby states.