STMicroelectronics STM1403CSNQ6F
- Part No.:
- STM1403CSNQ6F
- Manufacturer:
- STMicroelectronics
- Category:
- Supervisors
- Package:
- 16-VFQFN Exposed Pad
- Datasheet:
-
STM1403CSNQ6F.pdf
- Description:
- IC SUPERVISOR 1 CHANNEL 16QFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
STM1403CSNQ6F from STMicroelectronics is a FIPS-140 Level 3+ security supervisor IC for cryptographic module protection, featuring four high-impedance physical tamper inputs (TP1–TP4), over/under voltage detection (2.0 V / 4.2 V thresholds), and battery switchover with VCC-to-VBAT transition at ~2.4 V. It drives VOUT to ground during tamper events and provides open-drain SAL, RST, PFO, and BLD outputs - deployed in POS terminals and secure payment hardware.
For engineers reviewing the STM1403CSNQ6F datasheet, STM1403CSNQ6F pinout, STM1403CSNQ6F application, or STM1403CSNQ6F equivalent, key selection considerations include tamper response behavior (VOUT grounded on SAL), battery low detect threshold configurability (2.3 V / 2.5 V / 3.2 V), Vccsw logic state during alarm, and QFN16 3×3 mm package compatibility with secure PCB layout requirements.
Technical Context
The STM1403C implements dual-voltage monitoring: VINT (VCC or VBAT) is compared against VLV = 2.0 V (undervoltage) and VHV = 4.2 V (overvoltage) to trigger SAL. Tamper detection uses four independent inputs-TP1/TP3 (normally high, pulled low on intrusion) and TP2/TP4 (normally low, pulled high on intrusion)-with internal pull-up/pull-down options.
VOUT switching is controlled by VSW (~2.4 V): when VCC ≥ VSW, VOUT sourced from VCC; when VCC < VSW, VOUT sourced from VBAT. During SAL assertion, VOUT is actively driven to GND (distinguishing STM1403C from A/B variants), and Vccsw is forced high as a BATT ON indicator independent of VOUT state.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| FIPS-140 Level | Level 3+ certified - meets physical tamper resistance, voltage fault detection, and secure power management requirements for cryptographic modules. |
| Tamper Inputs | 4 independent pins (TP1–TP4) - TP1/TP3 NH (pull-low detection), TP2/TP4 NL (pull-high detection); no external bias required. |
| Voltage Monitoring | VCC/VBAT monitored for overvoltage (4.2 V typ) and undervoltage (2.0 V typ); triggers SAL regardless of power source. |
| Battery Switchover | VSW ≈ 2.4 V - automatic VOUT source switch from VCC to VBAT; supports lithium coin cell backup with low quiescent current (2.8 µA typ). |
| VOUT Tamper Response | Actively driven to GND on SAL assertion - enables direct reset or disable of external SRAM holding cryptographic keys. |
| Output Types | All critical outputs (SAL, RST, PFO, BLD) are open-drain - allows wired-OR interfacing and flexible voltage-level translation. |
| Package | QFN16, 3 mm × 3 mm, 0.5 mm pitch - low-profile, secure footprint with exposed thermal pad for PCB-level tamper sensing integration. |
Pinout & Package
STM1403CSNQ6F is housed in a secure, low-profile 16-pin QFN package (3 mm × 3 mm body, 0.5 mm pitch), optimized for anti-tampering PCB layouts with exposed thermal pad grounding and minimal trace exposure.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 2, 3, 4 | TP1–TP4 | Physical tamper inputs - TP1/TP3: normally high (NH); TP2/TP4: normally low (NL); each independently triggers SAL on state reversal. |
| 5 | VOUT | Main supply output - switches between VCC and VBAT; driven to GND during SAL for cryptographic SRAM disable. |
| 6 | VREF/VTPU | VTPU on STM1403C - internally switched VCC or VBAT; used for external tamper pull-up networks. |
| 7 | Vccsw | VCC switch status - low when VOUT sourced from VCC; high when VOUT sourced from VBAT; forced high during SAL. |
| 8 | MR | Manual reset input - active-low, internal 40 kΩ pull-up; asserts RST and holds it for 200 ms after release. |
| 9 | SAL | Security alarm output - open-drain, active-low; asserted on any tamper event or VINT out-of-range condition. |
| 10 | BLD | Battery low detect - open-drain, active-low during power-up if VBAT < VDET (configurable: 2.3/2.5/3.2 V). |
| 11 | PFI | Power-fail input - monitors external supply; triggers PFO low if VPFI threshold (~2.2 V) violated or VCC < VSW. |
| 12 | PFO | Power-fail output - open-drain, active-low; signals supply failure or VCC dropout before switchover. |
| 13 | RST | Reset output - open-drain, active-low; asserted when VCC < VRST (user-selectable) or MR low; 200 ms timeout. |
| 14 | VCC | Main supply input - powers device and sources VOUT until VCC drops below VSW (~2.4 V). |
| 15 | VBAT | Backup battery input - supplies VOUT and internal circuitry when VCC is invalid; supports 3 V lithium cells. |
| 16 | VSS | Ground reference - common return for all analog/digital functions; connects to exposed thermal pad. |
Key Features
| Feature | Design Value |
|---|---|
| Four independent tamper inputs | TP1/TP3 (NH) and TP2/TP4 (NL) enable flexible enclosure monitoring - no external resistors needed for basic operation. |
| VOUT forced to GND on tamper | Directly disables external SRAM or crypto controller power rail - eliminates need for external MOSFET or logic gate. |
| Configurable battery low detect | VDET selectable at 2.3 V / 2.5 V / 3.2 V - matches common lithium coin cell chemistries and accounts for diode drop. |
| Low quiescent current | 2.8 µA typical supply current - extends battery life in always-on secure systems without compromising detection speed. |
| Open-drain outputs with no internal pull-ups | SAL, RST, PFO, BLD allow shared bus use and level-shifting - avoids contention in multi-supervisor designs. |
Applications
| POS Terminal Security | EMV Payment Device |
|---|---|
|
Use Scenario: Tamper-evident housing for credit card readers with encrypted key storage. IC Role / Device Role / Timing Role: Security supervisor triggering immediate SRAM wipe and system shutdown upon enclosure breach or voltage fault. Use Value: VOUT driven to GND directly disables SRAM power, preventing key extraction; four tamper pins cover multiple access points. |
Use Scenario: Secure PIN entry device compliant with EMVCo and PCI PED standards. IC Role / Device Role / Timing Role: Monitors VCC/VBAT integrity and physical enclosure integrity to enforce cryptographic module lockdown. Use Value: FIPS-140 Level 3+ compliance achieved via simultaneous voltage monitoring and four independent tamper channels. |
| Secure Access Control Panel | Government ID Card Issuance System |
|
Use Scenario: Biometric door controller storing encryption keys in volatile memory. IC Role / Device Role / Timing Role: Battery-backed supervisor ensuring continuous tamper monitoring during mains outage. Use Value: Automatic VCC-to-VBAT switchover at ~2.4 V maintains supervision without interruption; BLD confirms battery health at power-up. |
Use Scenario: High-assurance smart card personalization station handling national ID data. IC Role / Device Role / Timing Role: Hardware root-of-trust component enforcing physical and electrical intrusion detection per ZKA guidelines. Use Value: Over/under voltage detection (2.0 V / 4.2 V) prevents fault injection attacks; SAL output integrates with host NMI line for instant response. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar security supervisor applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| STM1403ASNQ6F | VOUT remains ON (VCC or VBAT) during SAL; pin 9 = VREF (1.237 V); no VTPU function. | Suitable where external SRAM must remain powered during tamper for forensic logging. | Select only if VREF is required and VOUT grounding on alarm is not needed. |
| STM1403BSNQ6F | VOUT set to High-Z during SAL; pin 9 = VTPU; Vccsw forced high during alarm. | Used when external power path must be isolated rather than shorted or held active. | Choose when system requires tri-state VOUT control instead of GND forcing or continuous sourcing. |
Compared with STM1403CSNQ6F, the A variant preserves VOUT continuity for post-tamper diagnostics, while the B variant isolates VOUT entirely; the C variant's GND-driven VOUT provides strongest cryptographic key erasure assurance in SRAM-based systems.
Availability
STM1403CSNQ6F is available at Aetrix Electronics and suitable for POS terminal manufacturing, EMV payment device production, and government-issued ID card personalization systems requiring stable component supply and long-term lifecycle support.
Supply support for STM1403CSNQ6F includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader specializing in secure microcontrollers, power management, and automotive-grade ICs, with extensive expertise in cryptographic hardware design.
The STM1403 family targets FIPS-140 and EMVCo-compliant systems, delivering integrated tamper detection, voltage supervision, and battery switchover in a single secure QFN package.
FAQ
What is the VSW threshold for battery switchover?
The VSW threshold is approximately 2.4 V - when VCC falls below this value, the device automatically switches VOUT sourcing from VCC to VBAT. This value is fixed and not user-adjustable; it ensures reliable backup activation before main supply collapse, supporting standard 3 V lithium coin cells.
How does VOUT behavior differ between STM1403C and other variants during tamper?
During SAL assertion, STM1403C actively drives VOUT to GND - unlike STM1403A (VOUT remains ON) or STM1403B (VOUT goes High-Z). This GND forcing directly disables externally connected SRAM, enabling immediate cryptographic key erasure without additional circuitry.
Can TP1–TP4 be left unconnected?
No - unused tamper pins must be terminated: TP1/TP3 tied to VTPU (pin 6), TP2/TP4 tied to VSS. Floating these inputs risks false tamper alarms due to noise or leakage; the internal biasing is not sufficient for robust operation without proper external termination.
What is the purpose of the VTPU pin (pin 9) on STM1403C?
VTPU provides an internally switched version of VCC or VBAT - it follows the same source as VOUT and serves as a dedicated pull-up node for TP1/TP3 tamper circuits. Unlike STM1403A's VREF, it delivers no precision voltage but ensures consistent biasing across power domains during switchover.
STM1403CSNQ6F Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Series:
- -
- Package/Case:
- 16-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Type:
- Simple Reset/Power-On Reset
- Number of Voltages Monitored:
- 1
- Voltage - Threshold:
- 2.93V
- Output:
- Open Drain or Open Collector
- Reset:
- Active Low
- Reset Timeout:
- 140ms Minimum
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-QFN (3x3)
STM1403CSNQ6F FAQ
1.How can I place an order for STM1403CSNQ6F through Aetrix?
Please submit a Request for Quotation (RFQ) for STM1403CSNQ6F on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for STM1403CSNQ6F reliable?
The price and inventory of STM1403CSNQ6F are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for STM1403CSNQ6F is usually 5 days.
3.What payment methods are accepted for STM1403CSNQ6F?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for STM1403CSNQ6F transactions.
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4.How is shipping managed for STM1403CSNQ6F?
STM1403CSNQ6F orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your STM1403CSNQ6F order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for STM1403CSNQ6F?
For technical support, including STM1403CSNQ6F datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your STM1403CSNQ6F requirements.
6.How does Aetrix verify that STM1403CSNQ6F is sourced from the original manufacturer or authorized distributors?
All STM1403CSNQ6F products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that STM1403CSNQ6F meets industry standards.
7.What is the process for return or replacement of STM1403CSNQ6F?
All STM1403CSNQ6F units undergo pre-shipment inspection (PSI). If there is an issue with STM1403CSNQ6F, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The STM1403CSNQ6F part is unused and in its original packaging.
Return procedure for STM1403CSNQ6F:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
STM1403CSNQ6F Tags

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MIC826SYMT-TR
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APX803L20-29SA-7
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