My Inquiry
My Account
STMicroelectronics STM1404CSMJQ6F
- Part No.:
- STM1404CSMJQ6F
- Manufacturer:
- STMicroelectronics
- Category:
- Supervisors
- Package:
- 16-VFQFN Exposed Pad
- Datasheet:
-
STM1404CSMJQ6F.pdf
- Description:
- IC SUPERVISOR 1 CHANNEL 16QFN
- Quantity:
- Payment:
- Shipping:
Inventory:3,994
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
STM1404CSMJQ6F from STMicroelectronics is a FIPS-140 Level 4 security supervisor IC designed for cryptographic module protection in POS terminals and secure embedded systems. It provides four high-impedance physical tamper inputs (TP1–TP4), over/under voltage detection (2.0 V / 4.2 V thresholds), factory-programmable over/under temperature monitoring (–25°C to +95°C range), automatic battery switchover with Vccsw status indicator, and open-drain security alarm (SAL) output.
For engineers reviewing the STM1404CSMJQ6F datasheet, STM1404CSMJQ6F pinout, STM1404CSMJQ6F application, or STM1404CSMJQ6F equivalent, key selection criteria include tamper response behavior under SAL assertion (VOUT driven to ground), battery switchover threshold (~2.4 V), low quiescent current (5.3 µA typ), and QFN16 3 × 3 mm RoHS-compliant packaging for space-constrained secure modules.
Technical Context
The STM1404CSMJQ6F implements a dual-mode tamper detection architecture: physical intrusion sensing via four independent high-impedance inputs (TP1/TP3 NH, TP2/TP4 NL) and environmental monitoring using internal comparators for supply voltage (VINT) and die temperature (TA). Voltage thresholds are fixed at 2.0 V (undervoltage) and 4.2 V (overvoltage); temperature trip points (TL/TH) are factory-programmed per customer specification.
Its supervisory logic integrates battery switchover control with VOUT sourcing from VCC above ~2.4 V and from VBAT below that threshold. Upon SAL activation, the STM1404C variant forces VOUT to ground - a critical feature for disabling SRAM power in cryptographic modules - while Vccsw transitions high to signal battery backup mode.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Voltage Detection Thresholds | 2.0 V (undervoltage), 4.2 V (overvoltage); triggers SAL when VINT exceeds either limit |
| Battery Switchover Threshold | ~2.4 V; switches VOUT from VCC to VBAT when VCC falls below this level |
| Quiescent Supply Current | 5.3 µA typical; enables multi-year operation on coin-cell backup without compromising security monitoring |
| Tamper Input Configuration | TP1/TP3: normally high (NH); TP2/TP4: normally low (NL); all four pins support independent enclosure breach detection |
| VOUT Behavior on SAL | Driven to ground (STM1404C); ensures immediate power removal from external SRAM holding cryptographic keys |
| Package | QFN16, 3 mm × 3 mm, 0.5 mm pitch; low-profile, secure footprint compatible with tamper-evident PCB layouts |
| RoHS Compliance | Lead-free; meets EU Directive 2011/65/EU requirements for hazardous substance restriction |
Pinout & Package
STM1404CSMJQ6F is housed in a secure, low-profile 16-pin QFN package (3 mm × 3 mm, 0.5 mm pitch) with exposed thermal pad. Pin numbering follows standard QFN layout (pin 1 marked by dot; pins numbered counterclockwise).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 2, 3, 4 | TP1–TP4 | Physical tamper inputs: TP1/TP3 NH, TP2/TP4 NL; detect enclosure breach via state inversion |
| 5 | BLD | Battery low detect (open drain); active-low during power-up if VBAT < VDET (2.3/2.5/3.2 V options) |
| 6 | RST | Active-low reset output (open drain); asserted when VCC < VRST or MR pulled low |
| 7 | PFO | Power-fail output (open drain); goes low when PFI < VPFI or VCC < VSW |
| 8 | PFI | Power-fail input; monitors external supply rail for brownout conditions |
| 9 | VTPU | Tamper pull-up source (VCC or VBAT); supplies bias for TP1/TP3 when not using external resistors |
| 10 | VOUT | Supply voltage output; sourced from VCC (>2.4 V) or VBAT (<2.4 V); driven to ground on SAL for STM1404C |
| 11 | Vccsw | VCC switch output; low = VOUT sourced from VCC, high = VOUT sourced from VBAT (BATT ON indicator) |
| 12 | MR | Manual reset input (active-low); internal 40 kΩ pull-up; debounced via trec timing |
| 13 | SAL | Security alarm output (open drain); asserted low on any tamper event (voltage, temp, or physical) |
| 14 | VSS | Ground reference; must be connected to system common ground plane |
| 15 | VBAT | Backup battery supply input; powers device during main supply loss |
| 16 | VCC | Main supply input (2.4–3.6 V); powers device and charges backup path via internal diode |
Key Features
| Feature | Design Value |
|---|---|
| FIPS-140 Level 4 Compliance | Meets highest NIST-defined physical security tier via integrated tamper detection, voltage/temp monitoring, and alarm response |
| VOUT Grounding on Tamper | STM1404C-specific behavior: forces VOUT to GND upon SAL assertion, disabling SRAM power to prevent key extraction |
| Factory-Programmable Temp Thresholds | Lower (–25°C/–35°C) and upper (+80°C/+85°C/+95°C) limits set during manufacturing per customer requirement |
| Low-Power Tamper Monitoring | 5.3 µA typical supply current enables continuous monitoring without draining backup battery over extended periods |
| Open-Drain Alarm & Reset Outputs | SAL, RST, PFO, BLD all open-drain; allow wired-OR interfacing and flexible voltage-level translation in mixed-supply systems |
Applications
| POS Terminal Security Module | EMVCo-Compliant Payment Device |
|---|---|
|
Use Scenario: Tamper-proof housing for credit card transaction processing hardware with cryptographic key storage. IC Role / Device Role / Timing Role: Security supervisor detecting enclosure breach, voltage manipulation, or thermal attack; asserts SAL to disable SRAM and trigger secure erase. Use Value: Ensures FIPS-140 Level 4 compliance by grounding VOUT on tamper, cutting power to volatile memory containing encryption keys within microseconds. |
Use Scenario: Secure element integration in contactless payment terminals requiring EMVCo certification. IC Role / Device Role / Timing Role: Monitors environmental integrity during transaction execution; triggers SAL on out-of-spec voltage or temperature to halt cryptographic operations. Use Value: Prevents side-channel attacks by halting sensitive operations before tamper-induced data leakage occurs, meeting EMVCo physical security requirements. |
| Secure Industrial HSM | ZKA-Certified Banking Hardware |
|
Use Scenario: Hardware security module deployed in ATMs or kiosks operating in uncontrolled environments. IC Role / Device Role / Timing Role: Provides redundant tamper detection (4 physical inputs + voltage/temp sensors) with fail-safe VOUT grounding to isolate crypto engine. Use Value: Guarantees cryptographic key destruction on physical intrusion, satisfying ZKA and ISO/IEC 19790 tamper-response mandates. |
Use Scenario: German banking infrastructure requiring ZKA certification for PIN entry devices and secure vault controllers. IC Role / Device Role / Timing Role: Acts as primary security monitor enforcing mandatory voltage and temperature guardbands during cryptographic key loading and usage. Use Value: Enables ZKA certification by delivering factory-programmable trip points and deterministic SAL assertion within defined timing windows. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar security supervisor applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| STM1404BSMJQ6F | VOUT placed in high-impedance (High-Z) state on SAL assertion instead of grounded; VTPU pin used for tamper pull-up | Suitable where external circuitry requires isolation rather than forced discharge of VOUT rail | Select when system design uses external MOSFET switching and needs VOUT disconnection without grounding |
| STM1404ASMJQ6F | Includes 1.237 V reference output (VREF) on pin 9; VOUT remains powered (ON) during SAL assertion | Used where continuous power to monitored circuitry is required even during tamper events | Select when tamper response must preserve VOUT supply while signaling via SAL, e.g., for logging or controlled shutdown |
Compared with STM1404CSMJQ6F, the STM1404BSMJQ6F offers High-Z VOUT isolation for non-destructive tamper response, while the STM1404ASMJQ6F retains VOUT power and adds precision VREF - making the C variant uniquely suited for applications demanding irreversible SRAM power cutoff on intrusion.
Availability
STM1404CSMJQ6F is available at Aetrix Electronics and suitable for POS terminal security modules, EMVCo-certified payment devices, secure industrial HSMs, and ZKA-compliant banking hardware requiring stable component supply across long-lifecycle deployments.
Supply support for STM1404CSMJQ6F includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, analog ICs, power management devices, and security solutions for industrial, automotive, and consumer markets.
The STM1404 family belongs to ST's security supervision product line, engineered specifically to meet stringent physical and environmental intrusion detection requirements of FIPS-140, EMVCo, ISO/IEC 19790, and ZKA standards in cryptographic hardware.
FAQ
What is the function of the Vccsw pin on STM1404CSMJQ6F?
Vccsw indicates the active power source for VOUT: it is low when VOUT is supplied from VCC and high when VOUT is supplied from VBAT. During SAL assertion, Vccsw goes high - serving as a reliable "battery backup active" flag for system firmware or external monitoring circuits.
How does STM1404CSMJQ6F differ from STM1404ASMJQ6F and STM1404BSMJQ6F?
The STM1404C variant drives VOUT to ground on SAL assertion, whereas the A version keeps VOUT powered and the B version places VOUT in High-Z. Only the A version provides the 1.237 V VREF output. All three share identical pinout, tamper inputs, voltage/temp detection, and battery switchover logic.
Can STM1404CSMJQ6F operate with a 3.68 V lithium "AA" battery?
Yes - the BLD (battery low detect) function supports a 3.2 V VDET option (3.4 V – 0.2 V diode drop), making it compatible with 3.68 V lithium batteries. VCC must remain within 2.4–3.6 V; VBAT may exceed that range as long as internal diode drop is accounted for in design.
What are the factory-programmable temperature thresholds for STM1404CSMJQ6F?
Lower temperature limit (TL) is programmable to –25°C or –35°C; upper limit (TH) is programmable to +80°C, +85°C, or +95°C. These values are set during final test at ST's factory and cannot be modified in the field - ensuring immutable environmental tamper detection behavior.
STM1404CSMJQ6F Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Series:
- -
- Package/Case:
- 16-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Type:
- Simple Reset/Power-On Reset
- Number of Voltages Monitored:
- 1
- Voltage - Threshold:
- 2.93V
- Output:
- Open Drain or Open Collector
- Reset:
- Active Low
- Reset Timeout:
- 140ms Minimum
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-QFN (3x3)
STM1404CSMJQ6F FAQ
1.How can I place an order for STM1404CSMJQ6F through Aetrix?
Please submit a Request for Quotation (RFQ) for STM1404CSMJQ6F on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for STM1404CSMJQ6F reliable?
The price and inventory of STM1404CSMJQ6F are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for STM1404CSMJQ6F is usually 5 days.
3.What payment methods are accepted for STM1404CSMJQ6F?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for STM1404CSMJQ6F transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for STM1404CSMJQ6F?
STM1404CSMJQ6F orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your STM1404CSMJQ6F order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for STM1404CSMJQ6F?
For technical support, including STM1404CSMJQ6F datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your STM1404CSMJQ6F requirements.
6.How does Aetrix verify that STM1404CSMJQ6F is sourced from the original manufacturer or authorized distributors?
All STM1404CSMJQ6F products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that STM1404CSMJQ6F meets industry standards.
7.What is the process for return or replacement of STM1404CSMJQ6F?
All STM1404CSMJQ6F units undergo pre-shipment inspection (PSI). If there is an issue with STM1404CSMJQ6F, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The STM1404CSMJQ6F part is unused and in its original packaging.
Return procedure for STM1404CSMJQ6F:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
STM1404CSMJQ6F Tags
-
MIC826SYMT-TR
Microchip Technology
-
APX803S-31SA-7
Diodes Incorporated
-
APX803L20-29SA-7
Diodes Incorporated
-
TPS3828-33DBVR
Texas Instruments
-
V6340RSP3B+
EM Microelectronic
-
EM6325CXSP5B-2.9+
EM Microelectronic
-
MCP120T-300I/TT
Microchip Technology
-
MCP130T-315I/TT
Microchip Technology
-
MCP120T-475I/TT
Microchip Technology
-
MCP111T-300E/TT
Microchip Technology
-
MCP120T-315I/TT
Microchip Technology
-
MCP809T-315I/TT
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
