STMicroelectronics STM1404CTOCQ6F
- Part No.:
- STM1404CTOCQ6F
- Manufacturer:
- STMicroelectronics
- Category:
- Supervisors
- Package:
- 16-VFQFN Exposed Pad
- Datasheet:
-
STM1404CTOCQ6F.pdf
- Description:
- IC SUPERVISOR 1 CHANNEL 16QFN
- Quantity:
- Payment:

- Shipping:

Inventory:247
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Product details
Overview
STM1404CTOCQ6F from STMicroelectronics is a FIPS-140 Level 4 security supervisor IC designed for cryptographic module protection in POS terminals and secure embedded systems. It provides four high-impedance physical tamper inputs (TP1–TP4), over/under voltage detection (2.0 V / 4.2 V thresholds), factory-programmable over/under temperature monitoring (–25°C to +95°C range), automatic battery switchover with Vccsw status indicator, and open-drain SAL/RST/PFO/BLD outputs.
For engineers reviewing the STM1404CTOCQ6F datasheet, STM1404CTOCQ6F pinout, STM1404CTOCQ6F application, or STM1404CTOCQ6F equivalent, this device serves as a tamper-responsive power management and alarm controller for systems requiring certified physical intrusion detection, battery-backed SRAM retention, and secure reset supervision under FIPS-140-2/3 mandates.
Technical Context
The STM1404CTOCQ6F implements independent analog comparators for supply voltage (VINT) monitoring against programmable high/low thresholds (VLV = 2.0 V typ, VHV = 4.2 V typ), and dual temperature sensing with customer-defined trip points (TL = –25°C or –35°C; TH = +80°C, +85°C, or +95°C). Tamper detection logic triggers SAL on any violation across voltage, temperature, or four dedicated physical inputs (TP1–TP4), each configured as NH or NL with external switch/resistor networks.
Its battery switchover architecture monitors VCC vs. VSW (~2.4 V) and automatically routes VOUT from VCC to VBAT upon dropout, while asserting Vccsw high to indicate battery-on state. All critical outputs - SAL, RST, PFO, BLD - are open-drain with internal pull-downs or external pull-up requirements, enabling wired-OR alarm aggregation and flexible reset signaling.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Voltage Detection Thresholds | Undervoltage: 2.0 V typ; Overvoltage: 4.2 V typ - ensures operation within 3 V system rails and detects brown-out or overvoltage faults before cryptographic corruption. |
| Temperature Trip Points | Factory-programmed: TL = –25°C or –35°C; TH = +80°C, +85°C, or +95°C - enables precise environmental tamper response aligned with enclosure thermal profiles. |
| Battery Switchover Threshold | VSW ≈ 2.4 V - triggers seamless VOUT source transition from VCC to VBAT before main supply collapse, preserving SRAM contents. |
| Supply Current (Typ) | 5.3 µA at 3 V, 25°C - supports multi-year battery backup without compromising tamper detection readiness. |
| Reset Propagation Delay | trec = 200 ms typ after VCC rise above VRST - guarantees sufficient hold time for microcontroller initialization during recovery. |
| Physical Tamper Inputs | 4 independent pins (TP1–TP4): TP1/TP3 = normally high; TP2/TP4 = normally low - supports mesh, foil, or switch-based enclosure breach detection. |
| Output Drive Type | All alarm/reset outputs (SAL, RST, PFO, BLD) are open-drain - allows direct connection to shared interrupt lines or external pull-ups for voltage-level translation. |
Pinout & Package
STM1404CTOCQ6F is housed in a RoHS-compliant, secure low-profile 16-pin QFN package (3 mm × 3 mm, 0.5 mm pitch), optimized for tamper-resistant PCB layout with exposed thermal pad and minimal footprint.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 2, 3, 4 | TP1–TP4 | Independent physical tamper inputs: TP1/TP3 = NH (pull-down detection); TP2/TP4 = NL (pull-up detection) - configurable for switch/mesh/foil intrusion sensing. |
| 5 | BLD | Battery low detect output (open drain) - active-low during power-up if VBAT < VDET (2.3/2.5/3.2 V options), verifying backup integrity before secure boot. |
| 6 | RST | Active-low reset output (open drain) - asserts when VCC < VRST or MR is pulled low; holds for 200 ms post-recovery to ensure MCU reset completion. |
| 7 | PFO | Power-fail output (open drain) - goes low when PFI < VPFI or VCC < VSW, enabling early warning of supply collapse prior to switchover. |
| 8 | PFI | Power-fail input - monitors external rail or VCC via resistor divider; threshold VPFI is internally fixed and unadjusted. |
| 9 | VTPU | Tamper pull-up source (VCC or VBAT) - supplies bias for TP1/TP3 external resistors; not VREF (VREF is STM1404A-only). |
| 10 | VCCSW | VCC switch output - low when VOUT sourced from VCC; high when VOUT sourced from VBAT - serves as hardware "battery-on" indicator and MOSFET gate control. |
| 11 | VOUT | Switched supply output - delivers regulated 3 V system power from VCC or VBAT; remains active during SAL assertion in STM1404A variant (C suffix = ground during alarm). |
| 12 | SAL | Security alarm output (open drain) - active-low on any tamper event (voltage, temp, or TPx); primary signal for cryptographic module lockdown and NMI assertion. |
| 13 | MR | Manual reset input - active-low push-button interface with 40 kΩ internal pull-up; initiates RST assertion and clears pending alarms on release. |
| 14 | VBAT | Backup battery input - powers VOUT and internal circuitry when VCC fails; supports lithium coin cells (e.g., CR2032) with reverse-charge protection diode required. |
| 15 | VCC | Main supply input - powers device during normal operation; monitored for over/under voltage and used as VOUT source until VSW threshold crossed. |
| 16 | VSS | Ground reference - common return for all analog and digital functions; must be low-impedance and isolated from noisy digital planes in secure designs. |
Key Features
| Feature | Design Value |
|---|---|
| FIPS-140 Level 4 Compliance | Meets physical tamper resistance, environmental monitoring, and cryptographic module supervision requirements per NIST SP 800-140, including four independent tamper inputs and factory-programmable thresholds. |
| Four Configurable Tamper Inputs | TP1/TP3 (NH) and TP2/TP4 (NL) support diverse mechanical intrusion sensors - foil breaks, switch closures, or mesh continuity loss - without external logic. |
| Automatic Battery Switchover | VOUT transitions from VCC to VBAT at ~2.4 V with no software intervention; Vccsw pin signals source change, enabling external p-MOSFET control for >80 mA loads. |
| Open-Drain Alarm Architecture | SAL, RST, PFO, BLD outputs share wiring compatibility with existing interrupt buses and allow OR-ing of multiple security supervisors in hierarchical systems. |
| Low-Power Tamper Readiness | 5.3 µA typical quiescent current preserves multi-year battery life while maintaining full voltage/temperature/tamper monitoring capability at all times. |
Applications
| POS Terminal Security Module | EMVCo-Compliant Payment Device |
|---|---|
|
Use Scenario: Tamper-proof housing for credit card transaction processing with encrypted key storage in external SRAM. IC Role / Device Role / Timing Role: Security supervisor that monitors enclosure integrity (TP1–TP4), supply stability (VCC/VBAT), and ambient temperature, then asserts SAL to trigger immediate key erasure and RST to halt CPU execution. Use Value: Enables FIPS-140-2 Level 4 certification by providing hardware-enforced, zero-delay response to physical intrusion - preventing unauthorized access to cryptographic keys even during power loss. |
Use Scenario: Secure element in contactless payment terminals requiring continuous battery-backed memory retention and real-time environmental threat detection. IC Role / Device Role / Timing Role: Dual-role supervisor: manages VOUT switchover to preserve SRAM data during mains failure, and activates SAL on voltage/temperature excursions to initiate secure shutdown sequence. Use Value: Guarantees uninterrupted cryptographic session persistence and meets EMVCo requirement for tamper-responsive memory protection - eliminating need for external watchdog or discrete comparators. |
| Secure Industrial HSM | ZKA-Certified Banking Hardware |
|
Use Scenario: Hardware security module deployed in ATMs or kiosks operating in uncontrolled environments with wide temperature swings and potential physical attack vectors. IC Role / Device Role / Timing Role: Environmental monitor and power arbitrator: detects thermal anomalies (–25°C to +95°C range), validates battery health via BLD at power-up, and maintains VOUT during brownouts using Vccsw-controlled external MOSFET. Use Value: Provides certified, autonomous response to environmental tampering - satisfying ZKA and ISO 13491-2 requirements for banking-grade HSMs without firmware dependency. |
Use Scenario: German banking infrastructure device requiring ZKA certification for PIN entry devices (PEDs) with mandatory physical intrusion detection and secure boot verification. IC Role / Device Role / Timing Role: Certified tamper supervisor: uses factory-programmed TL/TH thresholds and four NH/NL inputs to detect enclosure breach, then drives SAL to disable cryptographic engine and assert RST to prevent compromised execution. Use Value: Delivers auditable, hardware-rooted tamper evidence generation and meets ZKA TR-03116 Section 4.2.3 for physical security enforcement - reducing validation effort for banking compliance. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar security supervisor applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MAX6956EAP+T | Provides 20-port I/O expander with integrated LED drivers and basic reset supervision, but lacks FIPS-140 Level 4 tamper inputs, temperature sensing, or battery switchover. | Targeted at general-purpose industrial control panels, not cryptographic modules requiring certified physical intrusion detection. | Select only if tamper detection is handled externally and system requires GPIO expansion alongside basic reset control. |
| TPS3808G33DBVR | Single-channel voltage supervisor with 3.3 V threshold and 200 ms reset delay, but no tamper inputs, temperature monitoring, or battery switchover capability. | Suitable for non-secure microcontroller reset supervision in consumer electronics, not for FIPS-140 or EMVCo applications. | Choose only for cost-sensitive, non-certified systems where voltage monitoring alone suffices and no physical security enforcement is required. |
Compared with MAX6956EAP+T and TPS3808G33DBVR, STM1404CTOCQ6F uniquely integrates FIPS-140 Level 4–compliant tamper detection, dual environmental monitoring, and autonomous battery switchover in a single QFN package - making it irreplaceable for certified cryptographic hardware where physical security is mandated.
Availability
STM1404CTOCQ6F is available at Aetrix Electronics and suitable for POS terminal security modules, EMVCo-compliant payment devices, secure industrial HSMs, and ZKA-certified banking hardware requiring stable component supply and long-term lifecycle assurance.
Supply support for STM1404CTOCQ6F includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader specializing in secure microcontrollers, power management, and automotive-grade ICs, with extensive expertise in cryptographic hardware and industrial safety certifications.
The STM1404 product line was developed specifically to address FIPS-140-2/3 and EMVCo physical security requirements for payment terminals and secure embedded systems - delivering certified tamper response, battery-backed operation, and environmental monitoring in a compact QFN package.
FAQ
What is the function of the Vccsw pin on STM1404CTOCQ6F?
Vccsw indicates the active power source for VOUT: it is low when VOUT is supplied from VCC, and high when VOUT is supplied from VBAT. This pin can drive an external p-channel MOSFET to handle >80 mA loads or serve as a hardware "battery-on" status signal. During SAL assertion, its behavior depends on variant - for STM1404C (C suffix), Vccsw goes high regardless of VOUT state.
How are the physical tamper inputs (TP1–TP4) configured and used?
TP1 and TP3 are normally high (NH) inputs, detecting tamper when pulled low via switch opening or foil breakage; TP2 and TP4 are normally low (NL), detecting tamper when pulled high. Each requires external biasing: NH pins connect to VTPU through ~10 MΩ resistors; NL pins connect to VSS. Unused pins must be tied accordingly - not left floating - to prevent false alarms.
Does STM1404CTOCQ6F provide a precision voltage reference?
No. STM1404CTOCQ6F uses pin 9 as VTPU (tamper pull-up source), not VREF. The 1.237 V reference is exclusive to the STM1404A variant. On STM1404C (indicated by 'C' in part number), pin 9 is VTPU and cannot generate a stable reference voltage - it switches between VCC and VBAT depending on switchover state.
What are the factory-programmable temperature thresholds for STM1404CTOCQ6F?
Lower temperature limit (TL) is factory-set to either –25°C or –35°C; upper limit (TH) is set to +80°C, +85°C, or +95°C. These values are permanently programmed during manufacturing and cannot be modified in-circuit. Selection occurs at order time via part number suffix and is documented in the device summary table of the datasheet.
STM1404CTOCQ6F Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Series:
- -
- Package/Case:
- 16-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Type:
- Simple Reset/Power-On Reset
- Number of Voltages Monitored:
- 1
- Voltage - Threshold:
- 3.08V
- Output:
- Open Drain or Open Collector
- Reset:
- Active Low
- Reset Timeout:
- 140ms Minimum
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-QFN (3x3)
STM1404CTOCQ6F FAQ
1.How can I place an order for STM1404CTOCQ6F through Aetrix?
Please submit a Request for Quotation (RFQ) for STM1404CTOCQ6F on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for STM1404CTOCQ6F reliable?
The price and inventory of STM1404CTOCQ6F are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for STM1404CTOCQ6F is usually 5 days.
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Once your STM1404CTOCQ6F order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for STM1404CTOCQ6F?
For technical support, including STM1404CTOCQ6F datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your STM1404CTOCQ6F requirements.
6.How does Aetrix verify that STM1404CTOCQ6F is sourced from the original manufacturer or authorized distributors?
All STM1404CTOCQ6F products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that STM1404CTOCQ6F meets industry standards.
7.What is the process for return or replacement of STM1404CTOCQ6F?
All STM1404CTOCQ6F units undergo pre-shipment inspection (PSI). If there is an issue with STM1404CTOCQ6F, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The STM1404CTOCQ6F part is unused and in its original packaging.
Return procedure for STM1404CTOCQ6F:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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