STMicroelectronics STM32F103R6T6
- Part No.:
- STM32F103R6T6
- Manufacturer:
- STMicroelectronics
- Category:
- Microcontrollers
- Package:
- 64-LQFP
- Datasheet:
-
STM32F103R6T6.pdf
- Description:
- IC MCU 32BIT 32KB FLASH 64LQFP
- Quantity:
- Payment:

- Shipping:

Inventory:3,777
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
STM32F103R6T6 from STMicroelectronics is a low-density performance-line ARM Cortex-M3 microcontroller with 32 KB Flash, 10 KB SRAM, and integrated USB 2.0 full-speed and CAN 2.0B interfaces. It operates at up to 72 MHz, features dual 12-bit ADCs (1 µs conversion), six timers including motor-control PWM with dead-time generation, and supports 51 I/Os in LQFP64 package. It is deployed in industrial motor control systems requiring real-time position feedback and communication over CAN bus.
For engineers reviewing the STM32F103R6T6 datasheet, STM32F103R6T6 pinout, STM32F103R6T6 application, or STM32F103R6T6 equivalent, key selection criteria include its 72 MHz Cortex-M3 core, USB+CAN dual-interface capability, 32 KB Flash/10 KB SRAM memory configuration, LQFP64 mechanical compatibility, and support for embedded real-time control with hardware CRC and 96-bit unique ID.
Technical Context
The STM32F103R6T6 implements an ARM Cortex-M3 core with Harvard architecture, single-cycle multiplication, and hardware divide, enabling deterministic interrupt latency and efficient real-time task scheduling. Its clock system integrates a 4–16 MHz external crystal oscillator, 8 MHz factory-trimmed internal RC, 40 kHz LSI, and PLL for CPU clock derivation - supporting precise timing for USB frame synchronization and CAN bit timing.
Peripheral integration includes two independent 12-bit ADCs with dual-sample-and-hold, enabling simultaneous sampling of motor phase currents; a 7-channel DMA controller servicing ADC, timers, SPI, I²C, and USARTs; and nested vectored interrupt controller (NVIC) with 68 interrupt channels for prioritized event handling in motion control loops.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | ARM Cortex-M3, 72 MHz max - enables 1.25 DMIPS/MHz real-time processing for closed-loop motor control without external co-processor. |
| Flash Memory | 32 KB - sufficient for bootloader + application firmware with USB DFU and CAN firmware update capability. |
| SRAM | 10 KB - supports dual-buffered ADC data acquisition, PID coefficient storage, and real-time stack for 6+ priority interrupts. |
| ADC Resolution | 12-bit, 1 µs conversion time - meets EN 61800-3 requirements for current sensing accuracy in Class A inverters. |
| Communication Interfaces | 1× USB 2.0 FS, 1× CAN 2.0B, 2× USART, 1× SPI, 1× I²C - enables host PC commissioning via USB and distributed node control via CAN bus. |
| Timers | 6 timers: 2× 16-bit general-purpose, 1× 16-bit motor-control PWM, 2× watchdogs, 1× SysTick - provides complementary PWM outputs with programmable dead-time for 3-phase inverter gate drivers. |
| I/O Count | 51 I/O pins, 5 V-tolerant on most - allows direct interface to 5 V logic sensors and industrial digital I/O without level shifters. |
| Supply Voltage | 2.0–3.6 V - compatible with standard 3.3 V LDOs and supports battery-backed RTC operation via VBAT pin. |
Pinout & Package
LQFP64 (10 × 10 mm, 0.5 mm pitch) package with exposed thermal pad; RoHS-compliant ECOPACK® construction. Pin count and layout match STM32F103x6 family for drop-in replacement across memory variants.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD, VSS | Power supply and ground | Dual VDD/VSS pairs ensure stable core and I/O rail decoupling; VDDA/VSSA separate analog domain for ADC reference integrity. |
| PA0–PA15, PB0–PB15, PC13–PC15 | General-purpose I/O | 51 total GPIOs mapped to 16 EXTI lines; most pins 5 V-tolerant - simplifies interfacing with legacy industrial sensors and actuators. |
| PA11/PA12 | USB D+/D− | Dedicated full-speed USB 2.0 transceiver pins - require 1.5 kΩ pull-up on D+ for device enumeration; no external PHY needed. |
| PB8/PB9 | CAN RX/TX | Dedicated CAN 2.0B physical layer interface - supports bit rates up to 1 Mbps with programmable sample point for robust fieldbus operation. |
| PA0, PA1 | ADC1_IN0 / ADC1_IN1 | Analog inputs for first ADC; shared with GPIO - enables simultaneous sampling of motor phase voltages or current shunt signals. |
| PA6/PA7, PB0/PB1 | TIM3_CH1–CH4 | Four-channel capture/compare outputs - configured as complementary PWM with dead-time insertion for 3-phase BLDC motor drive. |
| NRST | Active-low reset | Externally controllable reset input with internal pull-up; supports power-on reset, brown-out detection, and software-triggered system reset. |
Key Features
| Feature | Design Value |
|---|---|
| Hardware CRC calculation unit | Enables fast firmware image validation during boot or OTA updates - reduces flash read overhead vs. software CRC-32. |
| 96-bit unique device ID | Provides immutable serial number for secure device authentication and license binding in industrial gateway applications. |
| Temperature sensor | Integrated calibrated sensor (±1.5°C accuracy) - monitors die temperature for thermal derating of motor drive output stages. |
| Serial wire debug (SWD) | 2-pin debug interface replacing JTAG - preserves GPIO count while enabling full real-time trace and breakpoint debugging. |
| Programmable voltage detector (PVD) | Configurable threshold monitoring on VDD - triggers interrupt before brown-out, allowing graceful shutdown of motor control PWM outputs. |
Applications
| Industrial Motor Control | Smart Sensor Node |
|---|---|
Use Scenario: 3-phase BLDC motor drive in HVAC fan module with speed regulation and fault reporting. IC Role / Device Role / Timing Role: Main controller executing FOC algorithm, generating 6-channel complementary PWM, sampling current/voltage via dual ADC, and communicating status over CAN bus. Use Value: Integrated motor-control timer with dead-time insertion eliminates need for external gate driver logic; USB interface enables field calibration via PC tool. | Use Scenario: Wireless vibration sensor node with local FFT analysis and CAN-based alarm forwarding. IC Role / Device Role / Timing Role: Edge-processing MCU acquiring accelerometer data via SPI, running lightweight DSP routines in SRAM, and transmitting alerts via CAN 2.0B. Use Value: 10 KB SRAM supports double-buffered 1024-point FFT; 32 KB Flash stores firmware plus adaptive filter coefficients updated via CAN firmware download. |
| USB-Capable HMI Panel | Programmable Logic Controller (PLC) I/O Module |
Use Scenario: Touch-enabled operator panel with real-time diagnostics and firmware update capability. IC Role / Device Role / Timing Role: USB device controller hosting CDC ACM class for virtual COM port; manages display refresh, touch polling, and LED indicators via GPIO. Use Value: On-chip USB transceiver eliminates external PHY cost; 51 GPIOs support direct connection to resistive touch overlay and status LEDs without glue logic. | Use Scenario: DIN-rail mounted digital I/O expansion module with CAN backbone and isolated inputs/outputs. IC Role / Device Role / Timing Role: Central intelligence managing opto-isolated input scanning, relay coil drive timing, and CAN message framing for Modbus RTU gateway. Use Value: Independent watchdog ensures fail-safe relay de-energization; PVD detects supply sag before isolation barrier failure, triggering safe state transition. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| STM32F103C6T6 | LQFP48 package (48-pin), 32 KB Flash/10 KB SRAM, identical core/peripherals but 26 GPIOs instead of 51. | Suitable for space-constrained designs with fewer I/O needs; lacks CAN TX/RX dedicated pins in LQFP48 footprint. | Select when board layout requires smaller package and I/O count ≤26; verify CAN routing feasibility on 48-pin layout. |
| STM32F103VCT6 | LQFP100 package, 256 KB Flash/48 KB SRAM, same peripheral set plus additional timers, ADC channels, and communication interfaces. | Supports complex motion profiles with multi-axis interpolation and Ethernet-ready expansion via FSMC. | Choose for future-proofing or when application demands >32 KB code space and ≥80 GPIOs; requires PCB redesign for 100-pin footprint. |
Compared with STM32F103C6T6, the STM32F103R6T6 offers 25 more GPIOs and native CAN routing in LQFP64, making it optimal for distributed I/O systems; versus STM32F103VCT6, it trades memory scalability for lower BOM cost and simpler layout - ideal for cost-sensitive, fixed-function motor controllers.
Availability
STM32F103R6T6 is available at Aetrix Electronics and suitable for industrial motor control, smart sensor nodes, USB-capable HMI panels, and PLC I/O modules requiring stable component supply across extended production lifecycles.
Supply support for STM32F103R6T6 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power devices, sensors, and analog ICs for industrial, automotive, and consumer markets.
The STM32F103x6 series belongs to ST's mainstream Cortex-M3 portfolio, engineered specifically for cost-sensitive real-time control applications demanding USB connectivity, CAN bus integration, and deterministic interrupt response in harsh environments.
FAQ
What is the maximum operating frequency and associated power consumption of the STM32F103R6T6?
The STM32F103R6T6 achieves a maximum CPU frequency of 72 MHz with zero wait-state Flash access. At 3.3 V and 72 MHz, typical active current consumption is 36 mA (code from Flash, peripherals enabled), rising to 42 mA at 3.6 V. In Stop mode with regulator active, current drops to 12 µA at 25°C - verified per datasheet Table 16 and Figure 16.
Does the STM32F103R6T6 support USB device functionality without external components?
Yes - the part integrates a full-speed USB 2.0 transceiver with internal termination and pull-up resistor control. Only a 1.5 kΩ pull-up on PA12 (D+) is required for device enumeration; no external PHY, transceiver, or ESD protection diodes are mandatory for basic CDC or HID class operation per Section 2.3.20 and Figure 23 of the datasheet.
How many ADC channels can be simultaneously sampled, and what is the effective resolution in differential mode?
The STM32F103R6T6 contains two independent 12-bit ADCs, each supporting up to 16 external channels. Dual-sample-and-hold allows true simultaneous sampling of two signals (e.g., phase currents). While the ADC is inherently single-ended, external op-amp circuitry can implement pseudo-differential acquisition; the datasheet specifies ±1 LSB INL and ±1.5 LSB DNL - no native differential mode or hardware averaging is provided.
Is the STM32F103R6T6 pin-compatible with higher-memory variants like the STM32F103VCT6?
No - the STM32F103R6T6 uses LQFP64 packaging, while the STM32F103VCT6 uses LQFP100. Although both share identical peripheral signal naming and functional mapping, their pin counts, layouts, and power/ground pin distributions differ fundamentally. Migration requires PCB redesign; however, firmware is largely portable due to identical register maps and HAL library support.
STM32F103R6T6 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Package/Case:
- 64-LQFP
- Series:
- STM32F1
- Packaging:
- Tray
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Core Processor:
- ARM® Cortex®-M3
- Core Size:
- 32-Bit Single-Core
- Speed:
- 72MHz
- Connectivity:
- CANbus, I2C, IrDA, LINbus, SPI, UART/USART, USB
- Peripherals:
- DMA, Motor Control PWM, PDR, POR, PVD, PWM, Temp Sensor, WDT
- Number of I/O:
- 51
- Program Memory Size:
- 32KB (32K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 10K x 8
- Voltage - Supply (Vcc/Vdd):
- 2V ~ 3.6V
- Data Converters:
- A/D 16x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
STM32F103R6T6 FAQ
1.How can I place an order for STM32F103R6T6 through Aetrix?
Please submit a Request for Quotation (RFQ) for STM32F103R6T6 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for STM32F103R6T6 reliable?
The price and inventory of STM32F103R6T6 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for STM32F103R6T6 is usually 5 days.
3.What payment methods are accepted for STM32F103R6T6?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for STM32F103R6T6 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for STM32F103R6T6?
STM32F103R6T6 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your STM32F103R6T6 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for STM32F103R6T6?
For technical support, including STM32F103R6T6 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your STM32F103R6T6 requirements.
6.How does Aetrix verify that STM32F103R6T6 is sourced from the original manufacturer or authorized distributors?
All STM32F103R6T6 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that STM32F103R6T6 meets industry standards.
7.What is the process for return or replacement of STM32F103R6T6?
All STM32F103R6T6 units undergo pre-shipment inspection (PSI). If there is an issue with STM32F103R6T6, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The STM32F103R6T6 part is unused and in its original packaging.
Return procedure for STM32F103R6T6:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
STM32F103R6T6 Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

