STMicroelectronics STM32F105R8T6TR

Overview

STM32F105R8T6TR from STMicroelectronics is a 32-bit ARM Cortex-M3 microcontroller in LQFP64 package, featuring 64 KB Flash, 64 KB SRAM, dual CAN 2.0B interfaces, USB OTG FS with on-chip PHY, and 10/100 Ethernet MAC with IEEE 1588 support - deployed in industrial gateways requiring real-time protocol bridging and deterministic network timing.

For engineers reviewing the STM32F105R8T6TR datasheet, STM32F105R8T6TR pinout, STM32F105R8T6TR application, or STM32F105R8T6TR equivalent, key selection criteria include Ethernet MAC + dual CAN coexistence, USB OTG host/device capability, 72 MHz real-time execution, and 51 I/Os with 5 V tolerance for mixed-voltage system interfacing.

Technical Context

The device integrates a single ARM Cortex-M3 core with hardware division, 24-bit SysTick timer, and nested vectored interrupt controller (NVIC) supporting up to 80 interrupts. Its clock system includes 3–25 MHz HSE, 8 MHz factory-trimmed HSI, and 40 kHz LSI with calibration - enabling precise RTC operation and dynamic clock tree reconfiguration.

Connectivity peripherals are independently clocked and remappable: two CAN controllers share 512 bytes of dedicated SRAM; Ethernet MAC uses 4 KB dedicated SRAM and supports MII/RMII; USB OTG FS includes 1.25 KB SRAM and full HNP/SRP/ID negotiation - all operating concurrently without resource contention under DMA-driven data flow.

Key Specifications

Pinout & Package

LQFP64 (10 × 10 mm, 0.5 mm pitch) package with exposed thermal pad; RoHS-compliant, industrial temperature range (–40°C to +85°C).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar connectivity-focused microcontroller applications.

Compared with STM32F107VCT6, the STM32F105R8T6TR trades I/O count and Flash for compact LQFP64 footprint and lower power - ideal for space-constrained gateways. Versus STM32F407VGT6, it delivers deterministic dual-CAN/Ethernet latency without software-emulated MAC layers.

Availability

STM32F105R8T6TR is available at Aetrix Electronics and suitable for industrial gateways, automotive diagnostic tools, energy meter concentrators, and building management controllers requiring stable component supply across extended product lifecycles.

Supply support for STM32F105R8T6TR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, specializing in microcontrollers, power management, and sensing technologies for industrial, automotive, and consumer markets.

The STM32F105xx series belongs to ST's Connectivity Line - engineered specifically for embedded networking applications demanding simultaneous high-speed wired interfaces (Ethernet, USB, CAN) with real-time determinism and low-latency interrupt response.

FAQ

Does STM32F105R8T6TR support USB Device, Host, and OTG modes simultaneously?

Yes - the integrated USB OTG FS controller supports all three roles via software configuration. The on-chip PHY and 1.25 KB dedicated SRAM enable concurrent enumeration as device (e.g., CDC ACM) and host (e.g., HID keyboard) without external components, subject to descriptor and endpoint buffer constraints.

What is the maximum achievable CAN bit rate with STM32F105R8T6TR?

The CAN controllers support bit rates up to 1 Mbps under standard conditions (SJW=1, BS1=6, BS2=7, BRP=2 at 36 MHz APB1 clock). Electrical limits depend on transceiver and bus topology; ST's AN2830 confirms stable 800 kbps operation on 20 m twisted-pair cable with TJA1050.

Is the Ethernet MAC capable of full-duplex 100 Mbps operation?

Yes - the hardware supports full-duplex 100 Mbps with MII or RMII interface. It includes dedicated DMA channels, 4 KB SRAM for descriptors and packet buffers, and IEEE 1588 timestamp registers. PHY selection (e.g., LAN8720A) and PCB layout must meet IEEE 802.3u timing requirements.

How does the dual ADC interleaving mode improve sampling performance?

In interleaved mode, two 12-bit ADCs operate in staggered phases to achieve up to 2 MSPS aggregate throughput with 1 µs conversion time per channel. This enables synchronized acquisition of current/voltage pairs in motor control or simultaneous temperature/pressure readings in environmental monitoring.