STMicroelectronics STM32F105VCT6V
- Part No.:
- STM32F105VCT6V
- Manufacturer:
- STMicroelectronics
- Category:
- Microcontrollers
- Package:
- 100-LQFP
- Datasheet:
-
STM32F105VCT6V.pdf
- Description:
- IC MCU 32BIT 256KB FLASH 100LQFP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
STM32F105VCT6V from STMicroelectronics is a 32-bit ARM Cortex-M3 microcontroller in LQFP100 package, featuring 256 KB Flash, 64 KB SRAM, dual CAN 2.0B interfaces, USB OTG FS with on-chip PHY, and 10/100 Ethernet MAC with IEEE 1588 support - deployed in industrial gateways requiring real-time protocol bridging and deterministic network I/O.
For engineers reviewing the STM32F105VCT6V datasheet, STM32F105VCT6V pinout, STM32F105VCT6V application, or STM32F105VCT6V equivalent, key selection criteria include Ethernet+CAN coexistence, 72 MHz deterministic execution, 2×12-bit ADCs with temperature sensor, and SWD/JTAG debug support for field-upgradable edge controllers.
Technical Context
The STM32F105VCT6V integrates a single ARM Cortex-M3 core with Harvard bus architecture, 72 MHz max clock (0-wait-state Flash access), and hardware division/multiplication - enabling cycle-accurate control loops in motor drives and PLC I/O modules. Its nested vectored interrupt controller (NVIC) supports up to 80 GPIOs mapped to 16 external interrupt vectors, with nearly all pins 5 V-tolerant for mixed-voltage system interfacing.
It implements two independent CAN 2.0B controllers with 512 bytes of dedicated SRAM, a full-speed USB OTG FS controller with HNP/SRP/ID support and 1.25 KB SRAM, and a 10/100 Ethernet MAC with dedicated DMA, MII/RMII physical layer options, and IEEE 1588 hardware timestamping - enabling time-synchronized industrial Ethernet node design without external PHY or protocol offload.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Core | ARM Cortex-M3 @ 72 MHz; delivers 1.25 DMIPS/MHz for deterministic real-time task scheduling in motion control firmware. |
| Memory | 256 KB Flash + 64 KB SRAM; sufficient for dual-protocol stacks (CANopen + EtherCAT slave) plus application logic. |
| ADC | 2 × 12-bit, 1 µs converters (16 ch total); supports simultaneous sampling for current/voltage sensing in 3-phase inverters. |
| CAN Interfaces | 2 × CAN 2.0B controllers with 512 B dedicated SRAM; enables gateway operation between CAN FD legacy networks and Ethernet backbone. |
| Ethernet MAC | 10/100 Mbps with IEEE 1588 hardware timestamping and MII/RMII; eliminates need for external MAC/PHY in time-critical industrial Ethernet nodes. |
| USB Interface | USB OTG FS with on-chip PHY and 1.25 KB SRAM; supports device/host/OTG roles for firmware updates via USB stick or PC connection. |
| DAC | 2 × 12-bit DACs; provides analog setpoint outputs for PID loop reference generation or calibration signal injection. |
| Debug | SWD and JTAG interfaces + ETM trace macrocell; enables real-time instruction tracing and non-intrusive breakpoint debugging in safety-critical firmware. |
Pinout & Package
LQFP100 package (14 × 14 mm, 0.5 mm pitch), RoHS-compliant, operating temperature range –40 °C to +85 °C.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD, VSS | Power supply / Ground | Core and I/O supply pins; require separate decoupling (100 nF + 1 µF) per VDD pair for stable 72 MHz operation. |
| PA0–PA15, PB0–PB15, etc. | General-purpose I/O | 80 total GPIOs; 51 usable in LQFP100; all mappable to 16 EXTI lines and nearly all 5 V-tolerant for direct 5 V sensor interface. |
| PA11/PA12 | USB DP/DM | Dedicated full-speed USB OTG differential pair; internal pull-ups/downs configurable; no external transceiver needed. |
| PC1–PC4, PD8–PD15 | Ethernet MII signals | Supports MII interface (25 MHz RMII optional); includes ETH_MDC, ETH_MDIO, ETH_TXD[0:3], ETH_RXD[0:3], ETH_CRS, ETH_COL. |
| PB8/PB9, PD0/PD1 | CAN1/CAN2 TX/RX | Dual independent CAN transceiver interfaces; each with dedicated 256-byte SRAM buffer for mailbox-based message handling. |
| PA0, PA1 | ADC1_IN0 / ADC1_IN1 | Analog inputs for first 12-bit ADC; support sample-and-hold and temperature sensor channel (channel 16). |
Key Features
| Feature | Design Value |
|---|---|
| Remappable peripherals | All 14 communication interfaces (SPI/I2C/USART/CAN/USB/Ethernet) support full pinout remapping - simplifies PCB layout for EMI-sensitive industrial routing. |
| DMA controller | 12-channel DMA with peripheral-to-peripheral transfers; enables zero-CPU-load ADC→SRAM→Ethernet DMA chains for sensor data streaming. |
| CRC calculation unit | Hardware CRC-32 generator; accelerates firmware image integrity checks during over-the-air updates in connected devices. |
| Real-time clock (RTC) | 32 kHz oscillator with calibration; maintains time across Stop/Standby modes using VBAT; supports alarm and periodic wakeup at sub-second intervals. |
| Timers | 10 timers including 4×16-bit general-purpose, 1×16-bit motor control (dead-time insertion), and SysTick - supports encoder input, PWM generation, and precise timing for EtherCAT sync cycles. |
| Security ID | 96-bit unique device identifier fused at manufacture; used for secure boot key binding and anti-cloning in certified industrial equipment. |
Applications
| Industrial Ethernet Gateway | Automated Test Equipment (ATE) |
|---|---|
Use Scenario: Protocol translation between CAN-based fieldbus sensors and Modbus TCP/EtherNet/IP supervisory systems. IC Role / Device Role / Timing Role: Central MCU executing dual-stack firmware with real-time CAN message filtering and Ethernet frame assembly; IEEE 1588 timestamping synchronizes distributed I/O timestamps. Use Value: Eliminates external protocol bridge ICs; reduces BOM count by integrating CAN, Ethernet, and USB OTG in one die with shared memory and DMA. |
Use Scenario: High-precision stimulus/response instrumentation with synchronized analog capture and digital pattern generation. IC Role / Device Role / Timing Role: Dual 12-bit ADCs sample voltage/current waveforms at up to 2 MSPS (interleaved); 2×DACs generate calibrated reference signals; timers trigger acquisition with <100 ns jitter. Use Value: On-chip sample-and-hold and temperature sensor enable self-calibration routines without external components, improving measurement repeatability across temperature. |
| Motor Drive Controller | Building Automation Node |
Use Scenario: Compact servo drive controlling BLDC motors with field-oriented control (FOC) and safety monitoring. IC Role / Device Role / Timing Role: Executes FOC algorithm at 20 kHz PWM frequency; motor control timer generates complementary PWM with programmable dead-time; ADCs monitor phase currents in real time. Use Value: Integrated motor control timer with emergency stop input and hardware fault protection reduces external gate driver complexity and improves SIL-2 compliance path. |
Use Scenario: Smart HVAC controller managing zone dampers, CO₂ sensors, and BACnet/IP communication. IC Role / Device Role / Timing Role: Runs BACnet MSTP over RS-485 (via USART) and BACnet/IP over Ethernet simultaneously; RTC maintains schedule accuracy during power interruptions using VBAT. Use Value: Dual CAN and Ethernet interfaces allow concurrent integration into legacy building management systems (BMS) and modern IP-based infrastructure without gateway hardware. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar connectivity-focused microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| STM32F107VCT6 | Identical pinout and peripheral set, but rated only for industrial temperature range (–40 °C to +85 °C) vs. extended (–40 °C to +105 °C) for STM32F105VCT6V. | Not qualified for extended-temperature industrial enclosures or under-hood automotive auxiliary systems. | Select STM32F107VCT6 only if ambient operating temperature remains ≤85 °C and cost sensitivity outweighs thermal margin requirements. |
| STM32F407VGT6 | ARM Cortex-M4F core (168 MHz), FPU, larger Flash (1 MB), but lacks integrated Ethernet MAC - requires external PHY and increases BOM and layout complexity. | Suitable for compute-intensive tasks (e.g., FFT-based vibration analysis), but adds latency and component count for Ethernet-critical applications. | Choose only when floating-point math or higher code density justifies added Ethernet PHY cost and board space - not a drop-in replacement. |
Compared with STM32F107VCT6, the STM32F105VCT6V offers extended temperature qualification critical for harsh environments; versus STM32F407VGT6, it delivers lower-latency, lower-BOM Ethernet connectivity at the cost of computational headroom - making it optimal for deterministic protocol gateway designs.
Availability
STM32F105VCT6V is available at Aetrix Electronics and suitable for industrial gateways, motor drive controllers, automated test equipment, and building automation nodes requiring stable component supply across multi-year production cycles.
Supply support for STM32F105VCT6V includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power management ICs, sensors, and analog products for industrial, automotive, and consumer markets.
The STM32F105xx series belongs to ST's Connectivity Line - engineered specifically for embedded applications demanding integrated high-speed wired interfaces (Ethernet, USB OTG, dual CAN) without external protocol accelerators or PHYs.
FAQ
What is the maximum operating temperature rating for STM32F105VCT6V?
The STM32F105VCT6V is qualified for operation from –40 °C to +105 °C (industrial extended temperature grade), verified per ST's specification DocID15274 Rev 10, Section 5.3.1. This allows deployment in sealed enclosures with limited airflow or near heat-generating power stages without derating.
Does STM32F105VCT6V support IEEE 1588 Precision Time Protocol (PTP)?
Yes - the integrated Ethernet MAC includes hardware timestamping logic compliant with IEEE 1588-2008, enabling sub-microsecond packet timestamping on transmit/receive paths. No software timestamping or external PTP hardware is required for basic PTP slave implementation.
Can the USB OTG FS interface operate in host mode without external VBUS detection circuitry?
No - host mode requires external VBUS sensing and control. The STM32F105VCT6V provides only the USB transceiver and protocol engine; discrete components (e.g., VBUS comparator, power switch) must be added per ST Application Note AN2823 to safely manage VBUS negotiation and overcurrent protection.
How many CAN message mailboxes are available, and are they shared between CAN1 and CAN2?
The device provides 14 total mailboxes (128-bit each): 7 per CAN controller. Mailboxes are fully independent - CAN1 and CAN2 each have dedicated 512 bytes of SRAM and separate filter banks, enabling concurrent, isolated CAN traffic handling without arbitration or resource contention.
STM32F105VCT6V Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Package/Case:
- 100-LQFP
- Series:
- STM32F1
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Verified
- Core Processor:
- ARM® Cortex®-M3
- Core Size:
- 32-Bit Single-Core
- Speed:
- 72MHz
- Connectivity:
- CANbus, I2C, IrDA, LINbus, SPI, UART/USART, USB OTG
- Peripherals:
- DMA, POR, PWM, Voltage Detect, WDT
- Number of I/O:
- 80
- Program Memory Size:
- 256KB (256K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 64K x 8
- Voltage - Supply (Vcc/Vdd):
- 2V ~ 3.6V
- Data Converters:
- A/D 16x12b; D/A 2x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
STM32F105VCT6V FAQ
1.How can I place an order for STM32F105VCT6V through Aetrix?
Please submit a Request for Quotation (RFQ) for STM32F105VCT6V on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for STM32F105VCT6V reliable?
The price and inventory of STM32F105VCT6V are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for STM32F105VCT6V is usually 5 days.
3.What payment methods are accepted for STM32F105VCT6V?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for STM32F105VCT6V transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for STM32F105VCT6V?
STM32F105VCT6V orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your STM32F105VCT6V order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for STM32F105VCT6V?
For technical support, including STM32F105VCT6V datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your STM32F105VCT6V requirements.
6.How does Aetrix verify that STM32F105VCT6V is sourced from the original manufacturer or authorized distributors?
All STM32F105VCT6V products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that STM32F105VCT6V meets industry standards.
7.What is the process for return or replacement of STM32F105VCT6V?
All STM32F105VCT6V units undergo pre-shipment inspection (PSI). If there is an issue with STM32F105VCT6V, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The STM32F105VCT6V part is unused and in its original packaging.
Return procedure for STM32F105VCT6V:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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