STMicroelectronics STM32F405OEY6TR
- Part No.:
- STM32F405OEY6TR
- Manufacturer:
- STMicroelectronics
- Category:
- Microcontrollers
- Package:
- 90-UFBGA, WLCSP
- Datasheet:
-
STM32F405OEY6TR.pdf
- Description:
- IC MCU 32BIT 512KB FLASH 90WLCSP
- Quantity:
- Payment:

- Shipping:

Inventory:4,572
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
STM32F405OEY6TR from STMicroelectronics is a 32-bit Arm® Cortex®-M4 microcontroller with FPU, operating up to 168 MHz (210 DMIPS), featuring 512 KB flash, 192+4 KB SRAM (including 64 KB CCM), dual CAN 2.0B interfaces, USB OTG HS/FS, and 10/100 Ethernet MAC with IEEE 1588v2 support - deployed in industrial gateways requiring real-time protocol bridging and fieldbus-to-Ethernet convergence.
For engineers reviewing the STM32F405OEY6TR datasheet, STM32F405OEY6TR pinout, STM32F405OEY6TR application, or STM32F405OEY6TR equivalent, key selection criteria include its dual-CAN + Ethernet coexistence, 17-timer subsystem for motor control timing, DCMI camera interface (54 MB/s), ART Accelerator for zero-wait-state flash execution, and WLCSP90 package suitability for space-constrained edge nodes.
Technical Context
The STM32F405OEY6TR implements a tightly coupled Arm Cortex-M4 core with hardware FPU and DSP extensions, paired with the Adaptive Real-Time (ART) Accelerator enabling deterministic 168 MHz execution from embedded flash memory. Its multi-AHB bus matrix concurrently services CPU, DMA, and peripheral accesses without arbitration stalls.
It integrates dual independent CAN 2.0B controllers, a full-featured 10/100 Ethernet MAC with dedicated DMA and IEEE 1588v2 hardware timestamping, and a parallel digital camera interface (DCMI) supporting 8–14-bit YUV/RGB capture at up to 54 MB/s - all synchronized via a centralized RCC with multiple PLLs (main, audio, USB).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | Arm Cortex-M4 with FPU and DSP instructions; enables floating-point motion control and real-time signal processing without external coprocessor |
| Max Clock Frequency | 168 MHz with 210 DMIPS performance; supports hard real-time loop closure in servo drives and PLC scan cycles |
| Memory | 512 KB flash (0-wait-state via ART Accelerator), 192 KB main SRAM + 4 KB backup SRAM + 64 KB CCM RAM; CCM enables low-latency ISR/data buffers |
| Connectivity | Dual CAN 2.0B, USB 2.0 OTG HS/FS (with ULPI & on-chip PHY), 10/100 Ethernet MAC (MII/RMII, IEEE 1588v2 hardware timestamp) |
| Analog Peripherals | Three 12-bit ADCs (2.4 MSPS each, 7.2 MSPS interleaved), two 12-bit DACs, temperature sensor, and true RNG |
| Timers & I/O | Up to 17 timers (including advanced TIM1/TIM8), 140 GPIOs (138 5 V-tolerant), DCMI interface (54 MB/s), SDIO, and FSMC for NOR/NAND/PSRAM expansion |
Pinout & Package
STM32F405OEY6TR uses the WLCSP90 (4.223 × 3.969 mm) package - a wafer-level chip-scale package with 90 solder bumps, optimized for ultra-compact industrial IoT nodes and wearable edge controllers. Pin assignment follows ST's standardized ball map for STM32F405xx series, with VCAP_1/VCC/VSS distribution supporting stable core regulation under dynamic load.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD, VDDA, VDDUSB | Power supply inputs | Separate domains for digital core (1.8–3.6 V), analog (1.8–3.6 V), and USB PHY (3.3 V); enable noise isolation for ADC/DAC operation |
| VCAP_1, VCAP_2 | Core regulator decoupling | Must be connected to 2.2 µF X5R ceramic capacitors close to pins; critical for stable 1.2 V internal LDO output under 168 MHz switching |
| PA0–PA15, PB0–PB15, etc. | General-purpose I/O | 138 pins are 5 V-tolerant; allow direct interfacing with legacy 5 V logic, RS-485 transceivers, or industrial sensors without level shifters |
| PA11/PA12, PB14/PB15 | USB OTG FS/HS physical layer | PA11/PA12 = full-speed D+/D−; PB14/PB15 = high-speed ULPI data bus - require controlled impedance routing and ESD protection |
| PH13–PH15, PI0–PI10 | DCMI interface | Parallel 8–14-bit camera data bus (HSYNC/VSYNC/PCLK/D[0:13]); supports burst capture at 54 MB/s for machine vision preprocessing |
| PD8–PD15, PE2–PE7 | Ethernet MAC signals | MII/RMII interface (TX_EN, TXD[0:3], RXD[0:3], CRS, COL, REF_CLK); RMII mode reduces pin count to 9 signals for compact PHY integration |
Key Features
| Feature | Design Value |
|---|---|
| ART Accelerator | Eliminates flash wait states at 168 MHz, enabling deterministic ISR latency and real-time code execution directly from 512 KB embedded flash |
| CCM RAM | 64 KB core-coupled memory accessible only by CPU (not DMA); ideal for time-critical stack variables and interrupt handlers |
| Dual CAN + Ethernet | Simultaneous CAN FD-ready (2.0B) and IEEE 802.3-compliant Ethernet on single die - enables protocol gateway functionality without external bridge ICs |
| IEEE 1588v2 Hardware Support | Hardware timestamping engine in Ethernet MAC; achieves sub-1 µs clock synchronization accuracy for time-sensitive networking (TSN) applications |
| DCMI Interface | 8–14-bit parallel camera input with hardware cropping/scaling and JPEG encoder readiness; offloads image preprocessing from CPU |
Applications
| Industrial Protocol Gateway | Edge Vision Node |
|---|---|
Use Scenario: Bridging Modbus RTU (RS-485) and CANopen networks to EtherNet/IP or PROFINET over industrial Ethernet. IC Role / Device Role / Timing Role: Central protocol translation engine with dual CAN controllers, Ethernet MAC, and real-time OS scheduling on Cortex-M4+FPU. Use Value: Eliminates need for discrete bridge ICs or FPGA-based gateways; reduces BOM cost and PCB area while maintaining <100 µs inter-protocol latency. | Use Scenario: Low-power visual inspection unit in factory automation, capturing and preprocessing images from CMOS sensors before cloud upload. IC Role / Device Role / Timing Role: Camera interface controller (DCMI), real-time image buffer manager (CCM RAM), and JPEG-ready preprocessing accelerator. Use Value: 54 MB/s DCMI bandwidth and triple-interleaved ADC enable synchronized multi-sensor capture; ART Accelerator ensures consistent frame-rate processing from flash-resident firmware. |
| Motor Control Hub | Secure Field Controller |
Use Scenario: Compact servo drive controller managing position/velocity loops for BLDC motors using encoder feedback and PWM generation. IC Role / Device Role / Timing Role: Real-time motion controller with 17 timers (TIM1/TIM8 for complementary PWM), 3× ADCs for current sensing, and CAN for command interface. Use Value: 2.4 MSPS ADC sampling + 168 MHz core allows 20 kHz current-loop update rates; CCM RAM hosts PID coefficients for jitter-free execution. | Use Scenario: Tamper-resistant remote I/O module for SCADA systems, performing secure firmware updates and cryptographic authentication. IC Role / Device Role / Timing Role: Secure boot root-of-trust anchor with 96-bit unique ID, true RNG, and CRC calculation unit for firmware integrity verification. Use Value: On-chip RNG and hardware CRC accelerate SHA-256 signature validation; backup registers + VBAT support retain security state during brownout events. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| STM32F407VGT6 | LQFP100 package (14×14 mm), 1 MB flash, same peripherals but larger footprint and higher pin count | Better suited for prototyping and designs requiring more GPIOs or external memory expansion via FSMC | Select when board layout allows larger package and additional flash/SRAM is needed for complex protocol stacks |
| STM32H743ZIT6 | Arm Cortex-M7 core (480 MHz), dual-core option, 2 MB flash, enhanced crypto accelerators, no DCMI | Targeted at high-throughput AI inference at edge; lacks native camera interface but adds DSI and GPU-like capabilities | Choose for compute-intensive tasks where camera interface is secondary and cryptographic throughput is primary |
Compared with STM32F407VGT6, the STM32F405OEY6TR trades flash capacity and package size for ultra-compact WLCSP90 integration and lower system-level EMI; versus STM32H743ZIT6, it prioritizes deterministic real-time I/O (CAN/Ethernet/DCMI) over raw compute, with simpler power sequencing and lower static current in Stop mode.
Availability
STM32F405OEY6TR is available at Aetrix Electronics and suitable for industrial gateways, edge vision nodes, motor control hubs, and secure field controllers requiring stable component supply across extended product lifecycles.
Supply support for STM32F405OEY6TR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, specializing in microcontrollers, power management, sensors, and automotive ICs.
The STM32F4-series targets high-performance real-time embedded applications demanding rich connectivity, analog integration, and deterministic execution - especially in industrial automation, motor control, and human-machine interface systems.
FAQ
What is the maximum operating temperature range for STM32F405OEY6TR?
The STM32F405OEY6TR is rated for industrial temperature range: –40 °C to +85 °C ambient. This is validated per ST's DS8626 Rev 12 specification, with thermal derating applied above 70 °C for sustained 168 MHz operation. The WLCSP90 package's low thermal resistance (θJA ≈ 120 °C/W) requires careful PCB copper pour design to maintain junction temperature below 125 °C.
Does STM32F405OEY6TR support USB High-Speed device mode without an external PHY?
Yes - STM32F405OEY6TR integrates a dedicated USB 2.0 high-speed PHY and ULPI interface. It supports USB HS device mode natively using the on-chip PHY, eliminating need for external transceivers. However, HS host/OTG modes require external ULPI PHY connection (e.g., USB3300) per Section 3.31 of DS8626 Rev 12.
How many independent CAN controllers does STM32F405OEY6TR include, and are they CAN FD-capable?
The STM32F405OEY6TR integrates two independent bxCAN controllers compliant with ISO 11898-1:2015 (CAN 2.0B). They support classic CAN frames only - not CAN FD. Each controller features three transmission mailboxes, two receive FIFOs, and programmable filter banks. CAN FD capability was introduced in later STM32H7 and STM32G4 series.
Is the DCMI interface on STM32F405OEY6TR capable of supporting MIPI CSI-2 sensors?
No - the DCMI interface is a parallel 8–14-bit synchronous interface (HREF/VSYNC/PCLK + D[0:13]) and does not support MIPI CSI-2 serial protocol. Direct connection to MIPI sensors requires external bridge ICs (e.g., TC358743) or migration to STM32MP1/STM32H7 devices with native CSI-2 support. DCMI is optimized for OV-series parallel-output CMOS imagers.
STM32F405OEY6TR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Package/Case:
- 90-UFBGA, WLCSP
- Series:
- STM32F4
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- ARM® Cortex®-M4
- Core Size:
- 32-Bit Single-Core
- Speed:
- 168MHz
- Connectivity:
- CANbus, EBI/EMI, I2C, IrDA, LINbus, SPI, UART/USART, USB OTG
- Peripherals:
- Brown-out Detect/Reset, DMA, I2S, LCD, POR, PWM, WDT
- Number of I/O:
- 72
- Program Memory Size:
- 512KB (512K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 192K x 8
- Voltage - Supply (Vcc/Vdd):
- 1.8V ~ 3.6V
- Data Converters:
- A/D 13x12b; D/A 2x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
STM32F405OEY6TR FAQ
1.How can I place an order for STM32F405OEY6TR through Aetrix?
Please submit a Request for Quotation (RFQ) for STM32F405OEY6TR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for STM32F405OEY6TR reliable?
The price and inventory of STM32F405OEY6TR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for STM32F405OEY6TR is usually 5 days.
3.What payment methods are accepted for STM32F405OEY6TR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for STM32F405OEY6TR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for STM32F405OEY6TR?
STM32F405OEY6TR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your STM32F405OEY6TR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for STM32F405OEY6TR?
For technical support, including STM32F405OEY6TR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your STM32F405OEY6TR requirements.
6.How does Aetrix verify that STM32F405OEY6TR is sourced from the original manufacturer or authorized distributors?
All STM32F405OEY6TR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that STM32F405OEY6TR meets industry standards.
7.What is the process for return or replacement of STM32F405OEY6TR?
All STM32F405OEY6TR units undergo pre-shipment inspection (PSI). If there is an issue with STM32F405OEY6TR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The STM32F405OEY6TR part is unused and in its original packaging.
Return procedure for STM32F405OEY6TR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
STM32F405OEY6TR Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

