STMicroelectronics STM32F405VGT6J
- Part No.:
- STM32F405VGT6J
- Manufacturer:
- STMicroelectronics
- Category:
- Microcontrollers
- Package:
- 100-LQFP
- Datasheet:
-
STM32F405VGT6J.pdf
- Description:
- IC MCU 32BIT 1MB FLASH 100LQFP
- Quantity:
- Payment:

- Shipping:

Inventory:4,690
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
STM32F405VGT6J from STMicroelectronics is a 32-bit Arm® Cortex®-M4 microcontroller with FPU, operating up to 168 MHz (210 DMIPS), featuring 1 MB flash, 192+4 KB SRAM (including 64 KB CCM), dual CAN 2.0B interfaces, USB OTG HS/FS with dedicated DMA, and 10/100 Ethernet MAC with IEEE 1588v2 hardware support - deployed in industrial gateways requiring real-time protocol bridging and multi-interface edge processing.
For engineers reviewing the STM32F405VGT6J datasheet, STM32F405VGT6J pinout, STM32F405VGT6J application, or STM32F405VGT6J equivalent, key selection criteria include Ethernet + USB HS coexistence, triple 12-bit ADCs (7.2 MSPS interleaved), camera interface timing (54 MB/s), ART Accelerator-enabled zero-wait-state flash execution, and 138 5 V-tolerant I/Os for mixed-voltage system interfacing.
Technical Context
The STM32F405VGT6J integrates an Arm Cortex-M4 core with single-precision FPU and DSP instructions, coupled with ST's Adaptive Real-Time (ART) Accelerator enabling deterministic 0-wait-state execution from flash at 168 MHz. Its memory subsystem includes 1 MB of embedded flash, 192 KB main SRAM, 4 KB backup SRAM, and 64 KB CCM RAM tightly coupled to the CPU for low-latency data access.
Peripheral architecture features a multi-AHB bus matrix supporting concurrent high-bandwidth transfers: dedicated DMA channels for Ethernet MAC, USB OTG HS, SDIO, and DCMI; dual CAN controllers with time-triggered communication support; and a flexible static memory controller (FSMC) with NAND/NOR/PSRAM/CompactFlash™ compatibility - enabling direct connection to external displays, NOR flash boot devices, and industrial memory modules.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | Arm Cortex-M4 with FPU and DSP extensions, 168 MHz max frequency (210 DMIPS @ Dhrystone 2.1) |
| Memory | 1 MB flash (0-wait-state via ART Accelerator), 192 KB + 4 KB SRAM (64 KB CCM), 512 B OTP |
| ADC | Three 12-bit ADCs, up to 24 channels total, 7.2 MSPS in triple interleaved mode |
| Connectivity | Dual CAN 2.0B, USB 2.0 OTG HS/FS (dedicated DMA + on-chip PHY), 10/100 Ethernet MAC with IEEE 1588v2 hardware timestamping |
| Timers | Up to 17 timers: twelve 16-bit + two 32-bit general-purpose, plus advanced-control (TIM1/TIM8) with PWM/complementary outputs |
| I/O | Up to 140 GPIOs; 138 are 5 V-tolerant, 136 support up to 84 MHz toggle rate |
| Camera Interface | 8–14-bit parallel DCMI supporting up to 54 MB/s throughput for real-time image capture |
Pinout & Package
LQFP100 (14 × 14 mm, 0.5 mm pitch) package with exposed thermal pad; RoHS-compliant ECOPACK2 construction; 100-pin layout optimized for high-density industrial PCB routing with dedicated VCAP_1/VCAP_2 decoupling pins adjacent to VDD/VSS pairs.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD, VSS | Core power supply and ground | 1.8–3.6 V operation; requires local 2.2 µF ceramic + 100 nF bypass per VDD pair; VCAP_1/VCAP_2 pins connect to 2.2 µF external capacitors for internal regulator stability |
| PA0–PA15, PB0–PB15, etc. | General-purpose I/O banks | 138 pins 5 V-tolerant; all support interrupt capability; many multiplexed for AF functions (e.g., USART1_TX on PA9, CAN1_RX on PA11) |
| PH0/PH1 | HSE oscillator input/output | 4–26 MHz crystal connection; supports external clock source; critical for Ethernet/USB timing accuracy and RTC calibration |
| PC10/PC11/PC12 | SDIO interface | Direct connection to SD/SDIO/MMC cards; supports 4-bit wide data transfer at up to 48 MHz (HS mode) |
| PD0/PD1 | USART2 TX/RX | Asynchronous serial interface with LIN, IrDA, modem control, and ISO 7816 smartcard support - used for firmware updates and field diagnostics |
| PA12/PA11 | USB OTG FS D+/D− | Full-speed USB physical layer with integrated transceiver; no external PHY required; supports device/host/OTG roles |
| PA13/PA14/PA15 | SWD debug interface | Serial Wire Debug (SWD) only - JTAG disabled by default; enables low-pin-count in-circuit debugging and programming |
Key Features
| Feature | Design Value |
|---|---|
| ART Accelerator | Enables zero-wait-state execution from flash at 168 MHz, eliminating cache misses and guaranteeing deterministic interrupt latency for real-time control loops |
| CCM RAM | 64 KB core-coupled memory accessible only by CPU (not DMA), ideal for stack storage and time-critical ISR variables without bus contention |
| Dual CAN + Ethernet | Simultaneous CAN FD-capable (2.0B Active) and IEEE 802.3 10/100 MAC with MII/RMII support - enables protocol gateway designs bridging automotive CAN networks to IP-based SCADA systems |
| DCMI Interface | Hardware-synchronized 8–14-bit parallel camera input with FIFO and DMA handshaking, supporting up to 54 MB/s for VGA@60fps or QVGA@240fps streaming |
| True RNG | Digital true random number generator compliant with NIST SP800-90B, used for secure key generation in TLS/DTLS handshake and firmware signing verification |
Applications
| Industrial Protocol Gateway | Edge Vision Node |
|---|---|
|
Use Scenario: Field-deployed gateway connecting Modbus RTU sensors over RS-485 to cloud via Ethernet and MQTT. IC Role / Device Role / Timing Role: Central protocol translator with real-time scheduling, CAN/Ethernet timestamp synchronization, and dual-bank firmware update capability. Use Value: Dual CAN + Ethernet MAC with IEEE 1588v2 hardware timestamping ensures sub-microsecond alignment between sensor events and network packets. |
Use Scenario: Compact machine vision module capturing QR codes on production lines using CMOS image sensor. IC Role / Device Role / Timing Role: Image acquisition controller with DCMI interface, DMA-driven frame buffering, and JPEG compression offload via software libraries. Use Value: 54 MB/s DCMI bandwidth and triple interleaved ADC enable synchronized trigger-and-capture of optical encoder feedback alongside image frames. |
| Secure IoT Edge Controller | Multi-Interface HMI Platform |
|
Use Scenario: Tamper-resistant remote terminal unit (RTU) performing encrypted telemetry uploads over cellular + Ethernet failover. IC Role / Device Role / Timing Role: Secure boot root-of-trust anchor with 96-bit unique ID, true RNG, and hardware-accelerated AES via Crypto processor peripherals. Use Value: On-chip true RNG and 96-bit UID enable cryptographically secure device identity binding for zero-touch provisioning and certificate enrollment. |
Use Scenario: Human-machine interface panel integrating resistive touchscreen, audio playback, and serial control of PLCs. IC Role / Device Role / Timing Role: Application processor managing LCD parallel interface (8080 mode), I2S audio output, and multiple UARTs for peripheral coordination. Use Value: LCD parallel interface with 8080/6800 modes and 2×12-bit DACs allow direct drive of monochrome graphic displays and analog audio output without external converters. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar high-performance MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| STM32F407VGT6 | Same core, memory, and peripherals; differs only in Ethernet PHY integration - includes internal 10/100 PHY, while STM32F405VGT6J lacks it and requires external PHY | Eliminates need for external Ethernet PHY chip; reduces BOM count but increases package thermal load | Select when minimizing external components for Ethernet connectivity is prioritized over PHY flexibility and thermal budget |
| STM32H743VIT6 | Higher performance (480 MHz Cortex-M7, dual-core option), larger memory (2 MB flash, 1 MB RAM), enhanced security (AES/HASH/SHA, PKA), but no native USB HS PHY - requires ULPI interface | Supports complex real-time OS workloads and cryptographic acceleration; not drop-in compatible due to different pinout and voltage requirements | Select when future-proofing for AI inference preprocessing, secure bootchain expansion, or higher-resolution display rendering is required |
Compared with STM32F407VGT6, the STM32F405VGT6J trades integrated Ethernet PHY for greater signal integrity control and lower thermal density; versus STM32H743VIT6, it offers proven maturity, simpler power sequencing, and full USB HS PHY integration - making it optimal for cost-sensitive, thermally constrained industrial gateways needing dual-CAN + Ethernet coexistence.
Availability
STM32F405VGT6J is available at Aetrix Electronics and suitable for industrial protocol gateways, edge vision nodes, secure IoT controllers, and multi-interface HMI platforms requiring stable component supply across extended product lifecycles.
Supply support for STM32F405VGT6J includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, specializing in microcontrollers, power management, sensors, and automotive ICs with vertical manufacturing and broad industrial qualification coverage.
The STM32F4 series targets high-performance embedded applications demanding real-time responsiveness, rich connectivity, and deterministic execution - designed specifically for industrial automation, motor control, medical instrumentation, and networked edge devices.
FAQ
What is the maximum operating frequency and how is it achieved?
The STM32F405VGT6J achieves 168 MHz maximum CPU frequency using its Arm Cortex-M4 core with FPU, enabled by ST's Adaptive Real-Time (ART) Accelerator. This logic block pre-fetches and caches instructions from flash, eliminating wait states even at full speed. The system clock derives from the main PLL, which accepts input from HSE (4–26 MHz crystal) or HSI (16 MHz RC), and must be configured with appropriate flash wait states and voltage scaling (VOS range 1) to sustain 168 MHz operation.
Does this part support USB High-Speed device/host functionality without external components?
Yes - the STM32F405VGT6J integrates a full USB 2.0 High-Speed (480 Mbps) PHY with ULPI interface and dedicated DMA controller. It supports HS device/host/OTG roles without requiring external transceivers. However, external ULPI PHY components (e.g., SMSC USB334x) are needed only if using ULPI mode instead of the internal PHY; the internal PHY is enabled by default and requires only standard USB connector routing and ESD protection.
How many independent CAN interfaces does it provide, and what protocol versions are supported?
The STM32F405VGT6J provides two fully independent bxCAN controllers (CAN1 and CAN2), each compliant with ISO 11898-1:2015 (CAN 2.0B Active). Both support standard (11-bit) and extended (29-bit) identifiers, programmable bit timing, automatic retransmission, and loopback/self-test modes. Neither supports CAN FD; for FD capability, STM32H7 or STM32G4 series parts are required.
What is the role of the CCM (core-coupled memory), and how is it accessed?
The 64 KB CCM (core-coupled memory) is a tightly coupled SRAM block accessible exclusively by the Cortex-M4 CPU - not by DMA or other bus masters. It provides zero-wait-state, low-latency storage for critical code sections (e.g., ISRs) and stack variables, avoiding AHB bus contention. It is mapped to address 0x10000000 and can be enabled via SYSCFG_MEMRMP register; its use requires explicit linker script placement and compiler attributes (e.g., __attribute__((section(".ccmram")))).
STM32F405VGT6J Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Package/Case:
- 100-LQFP
- Series:
- STM32F4
- Packaging:
- Tray
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Core Processor:
- ARM® Cortex®-M4
- Core Size:
- 32-Bit Single-Core
- Speed:
- 168MHz
- Connectivity:
- CANbus, EBI/EMI, I2C, IrDA, LINbus, SPI, UART/USART, USB OTG
- Peripherals:
- Brown-out Detect/Reset, DMA, I2S, LCD, POR, PWM, WDT
- Number of I/O:
- 82
- Program Memory Size:
- 1MB (1M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 192K x 8
- Voltage - Supply (Vcc/Vdd):
- 1.8V ~ 3.6V
- Data Converters:
- A/D 16x12b; D/A 2x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
STM32F405VGT6J FAQ
1.How can I place an order for STM32F405VGT6J through Aetrix?
Please submit a Request for Quotation (RFQ) for STM32F405VGT6J on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for STM32F405VGT6J reliable?
The price and inventory of STM32F405VGT6J are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for STM32F405VGT6J is usually 5 days.
3.What payment methods are accepted for STM32F405VGT6J?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for STM32F405VGT6J transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for STM32F405VGT6J?
STM32F405VGT6J orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your STM32F405VGT6J order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for STM32F405VGT6J?
For technical support, including STM32F405VGT6J datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your STM32F405VGT6J requirements.
6.How does Aetrix verify that STM32F405VGT6J is sourced from the original manufacturer or authorized distributors?
All STM32F405VGT6J products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that STM32F405VGT6J meets industry standards.
7.What is the process for return or replacement of STM32F405VGT6J?
All STM32F405VGT6J units undergo pre-shipment inspection (PSI). If there is an issue with STM32F405VGT6J, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The STM32F405VGT6J part is unused and in its original packaging.
Return procedure for STM32F405VGT6J:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
STM32F405VGT6J Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

