STMicroelectronics STM32F446ZEH7TR
- Part No.:
- STM32F446ZEH7TR
- Manufacturer:
- STMicroelectronics
- Category:
- Microcontrollers
- Package:
- 144-UFBGA
- Datasheet:
-
STM32F446ZEH7TR.pdf
- Description:
- IC MCU 32BIT 512KB FLSH 144UFBGA
- Quantity:
- Payment:

- Shipping:

Inventory:1,893
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
STM32F446ZEH7TR from STMicroelectronics is a 32-bit Arm® Cortex®-M4 microcontroller with FPU, operating up to 180 MHz (225 DMIPS), featuring 512 KB flash, 128+4 KB RAM, dual USB OTG (FS/HS), three 12-bit ADCs (7.2 MSPS in triple interleaved mode), and two CAN 2.0B interfaces - deployed in industrial motor control and audio gateway systems.
For engineers reviewing the STM32F446ZEH7TR datasheet, STM32F446ZEH7TR pinout, STM32F446ZEH7TR application, or STM32F446ZEH7TR equivalent, key selection criteria include USB HS/FS dual-role capability, 114 GPIOs with 90 MHz toggle rate, QuadSPI + FMC for external memory expansion, and hardware-accelerated audio interfaces (SAI, SPDIFRX, I2S) supporting real-time audio processing.
Technical Context
The device integrates an Adaptive Real-time Accelerator (ART Accelerator™) enabling zero-wait-state execution from flash at 180 MHz, alongside a multi-AHB bus matrix for concurrent peripheral access. Its clock system includes dual PLLs (main PLL, PLLI2S, PLLSAI) supporting independent audio and system clock domains.
It implements a flexible low-power architecture with Sleep/Stop/Standby modes, VBAT-backed RTC and 4 KB backup SRAM, and advanced analog subsystems: triple 12-bit ADCs with hardware interleaving, two 12-bit DACs, and integrated temperature sensor - all synchronized via shared trigger sources and DMA channels.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Core | Arm Cortex-M4 with FPU, 180 MHz max frequency → enables real-time DSP algorithms (e.g., motor FOC, audio FFT) without external co-processor |
| Flash / RAM | 512 KB flash + 128 KB SRAM + 4 KB backup SRAM → supports complex firmware with OTA update partitioning and non-volatile context retention |
| ADC Performance | 3× 12-bit ADCs, 7.2 MSPS in triple interleaved mode → captures synchronized multi-channel analog signals (e.g., 3-phase motor currents) at sub-microsecond resolution |
| USB Connectivity | Dual USB OTG: FS controller with on-chip PHY + HS controller with dedicated DMA and ULPI support → enables simultaneous host/device roles and high-bandwidth data streaming (e.g., USB audio class) |
| Audio Interfaces | 2× SAI, SPDIF-RX, 3× I2S-capable SPI, PLLI2S/PLLSAI → provides full-duplex, multi-channel, sample-accurate audio I/O for professional audio equipment |
| Timers & PWM | Up to 17 timers including 2× advanced-control (TIM1/TIM8) with dead-time insertion and complementary outputs → supports 3-phase inverter gate driving with hardware safety features |
| Communication Peripherals | 2× CAN 2.0B, 4× USART, 4× I2C, SDIO, CEC → enables robust fieldbus integration (CANopen), legacy serial protocols (LIN, IrDA), and multimedia card interfacing |
Pinout & Package
LQFP144 (20 × 20 mm) package with 114 user I/O pins, 5 V-tolerant on 112 pins, and dedicated power/ground distribution for analog/digital separation and EMI suppression.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDDA/VSSA | Analog power supply/ground | Independent 1.7–3.6 V domain for ADC/DAC/temperature sensor - must be filtered separately to maintain 12-bit linearity |
| PA0–PA15, PB0–PB15, etc. | General-purpose I/O | Configurable as GPIO, AF functions (e.g., TIMx_CHy, USARTx_TX), or event inputs - 90 MHz toggle rate supports high-speed bit-banging or encoder input capture |
| PC10/PC11/PC12 | USB HS ULPI interface | 8-bit parallel data + CLK, DIR, NXT, STP signals - requires controlled impedance routing and termination for 60 MHz ULPI timing compliance |
| PD0/PD1 | OSC_IN/OSC_OUT | 4–26 MHz crystal oscillator connection - mandates load capacitance matching per crystal spec (typically 12–18 pF) for stable 180 MHz system clock |
| PF0–PF15 | FMC address/data bus | Supports NOR/NAND/SDRAM interfacing - enables external program execution or large buffer storage (e.g., audio sample buffering) |
Key Features
| Feature | Design Value |
|---|---|
| ART Accelerator™ | Enables 0-wait-state 180 MHz execution from flash - eliminates need for external SRAM caching in cost-sensitive designs |
| Dual USB OTG controllers | Independent FS (on-chip PHY) and HS (ULPI + dedicated DMA) paths - allows simultaneous USB device (CDC ACM) and host (mass storage) operation |
| Triple ADC interleaving | Hardware-synchronized sampling across 3 ADCs with shared DMA burst transfer - achieves effective 7.2 MSPS on single channel without CPU intervention |
| Flexible memory controller (FMC) | 16-bit data bus supporting SDRAM, PSRAM, NOR/NAND - enables >1 MB external RAM for real-time waveform generation or video frame buffers |
| SAI + SPDIFRX + I2S | Three independent audio interfaces with separate clocks and FIFOs - supports simultaneous I2S playback, SPDIF input, and SAI loopback for latency-critical audio routing |
Applications
| Industrial Motor Control | Professional Audio Gateway |
|---|---|
Use Scenario: Closed-loop control of 3-phase BLDC/PMSM motors in HVAC compressors and servo drives. IC Role / Device Role / Timing Role: Real-time execution of Field-Oriented Control (FOC) algorithm, synchronized ADC sampling of phase currents, and PWM generation with <100 ns dead-time precision. Use Value: Advanced-control timers (TIM1/TIM8) with break-input protection and hardware-triggered ADC conversions ensure safe, jitter-free motor commutation at 20 kHz switching frequency. | Use Scenario: Multi-format audio bridge between AES/EBU digital inputs, USB audio class devices, and analog line outputs. IC Role / Device Role / Timing Role: Simultaneous SPDIF-RX decoding, USB audio streaming (ASRC + FIFO management), and I2S output to DAC - all time-aligned via common audio clock tree. Use Value: Dual PLLs (PLLI2S + PLLSAI) generate independent, phase-locked clocks for each audio domain, eliminating sample-rate conversion artifacts in pro-audio signal chains. |
| Medical Diagnostic Imaging Interface | Automotive Body Control Module (BCM) |
Use Scenario: High-speed acquisition and preprocessing of ultrasound echo data from analog front-end (AFE) arrays. IC Role / Device Role / Timing Role: DCMI parallel camera interface capturing 8–14-bit pixel streams at 54 MB/s, coupled with DMA-driven FFT processing in SRAM. Use Value: 114 fast I/Os and hardware CRC unit enable real-time checksum validation of raw image frames before compression or display rendering. | Use Scenario: Centralized vehicle subsystem management including door lock actuation, window lift control, and interior lighting dimming. IC Role / Device Role / Timing Role: CAN 2.0B communication hub interfacing with LIN slaves, PWM-controlled LED drivers, and wake-on-CAN event handling in Stop mode. Use Value: VBAT-supplied RTC and 20×32-bit backup registers retain security keys and fault logs during battery disconnect, meeting ISO 16750-2 cold-cranking requirements. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| STM32F429ZIT6 | Includes LCD-TFT controller (no DCMI); same core/peripherals but lacks SPDIFRX and has lower USB HS bandwidth (no dedicated DMA) | Better suited for HMI-centric designs requiring embedded display; less optimal for audio-focused or camera-based edge sensing | Select when display interface is primary requirement and SPDIF/audio precision is secondary |
| STM32H743ZIT6 | Cortex-M7 core (480 MHz), dual-core option, higher flash/RAM, but no SPDIFRX and larger package (LQFP144 same footprint but different pinout) | Targets AI inference + real-time control fusion; incompatible pin-for-pin due to remapped ADC/USB/CAN signals | Choose for compute-intensive workloads where migration effort is acceptable and SPDIFRX is not required |
Compared with STM32F429ZIT6, the STM32F446ZEH7TR delivers superior audio interface fidelity and deterministic USB HS throughput, while versus STM32H743ZIT6 it offers pin-compatible upgrade path within F4 family toolchains and lower BOM cost for audio/motor applications without M7-level compute demand.
Availability
STM32F446ZEH7TR is available at Aetrix Electronics and suitable for industrial motor control, professional audio gateways, medical imaging interfaces, and automotive body control modules requiring stable component supply across extended product lifecycles.
Supply support for STM32F446ZEH7TR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power ICs, sensors, and analog components for industrial, automotive, and consumer markets.
The STM32F4 series targets high-performance embedded applications demanding real-time signal processing, rich connectivity, and deterministic low-latency peripherals - optimized for cost-sensitive industrial automation and audio/video edge devices.
FAQ
What is the maximum operating frequency and how is it achieved?
The STM32F446ZEH7TR achieves 180 MHz maximum CPU frequency using its internal main PLL driven by either the 4–26 MHz HSE crystal or 16 MHz HSI RC oscillator. The ART Accelerator™ enables zero-wait-state execution from flash memory at this speed, validated across voltage (1.7–3.6 V) and temperature (–40°C to +105°C) ranges per DS10693 Rev 11 Section 6.3.1.
Does this MCU support external SDRAM, and what interface is used?
Yes, the STM32F446ZEH7TR supports external SDRAM via its Flexible Memory Controller (FMC) with 16-bit data bus and dedicated control signals (BA0/BA1, RAS, CAS, WE, CLK). It complies with JEDEC-standard SDR SDRAM (not DDR), with timing parameters specified in DS10693 Rev 11 Table 6.3.26 and supported clock frequencies up to 90 MHz.
How many ADC channels can be simultaneously sampled with hardware synchronization?
All 24 ADC channels across the three 12-bit ADCs (ADC1–ADC3) can be hardware-synchronized using the triple interleaved mode, achieving up to 7.2 MSPS aggregate sampling rate. This requires configuration of shared trigger sources (e.g., TIM8 TRGO) and DMA burst transfers - detailed in RM0390 Section 14.3.17 and DS10693 Section 3.37.
Is the USB HS interface compatible with ULPI PHYs from multiple vendors?
Yes, the USB HS interface conforms to the UTMI+ Level 3 specification and supports standard ULPI v1.1 PHYs (e.g., SMSC USB334x, Microchip USB3300). Pin assignments (D0–D7, CLK, DIR, NXT, STP) match ULPI timing requirements, and electrical characteristics (VIH/VIL, drive strength) are verified per DS10693 Section 6.3.20 and AN4879 application note.
STM32F446ZEH7TR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Package/Case:
- 144-UFBGA
- Series:
- STM32F4
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- ARM® Cortex®-M4
- Core Size:
- 32-Bit Single-Core
- Speed:
- 180MHz
- Connectivity:
- CANbus, EBI/EMI, I2C, IrDA, LINbus, SAI, SD, SPDIF-Rx, SPI, UART/USART, USB, USB OTG
- Peripherals:
- Brown-out Detect/Reset, DMA, I2S, LVD, POR, PWM, WDT
- Number of I/O:
- 114
- Program Memory Size:
- 512KB (512K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 132K x 8
- Voltage - Supply (Vcc/Vdd):
- 1.7V ~ 3.6V
- Data Converters:
- A/D 24x12b; D/A 2x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
STM32F446ZEH7TR FAQ
1.How can I place an order for STM32F446ZEH7TR through Aetrix?
Please submit a Request for Quotation (RFQ) for STM32F446ZEH7TR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for STM32F446ZEH7TR reliable?
The price and inventory of STM32F446ZEH7TR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for STM32F446ZEH7TR is usually 5 days.
3.What payment methods are accepted for STM32F446ZEH7TR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for STM32F446ZEH7TR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for STM32F446ZEH7TR?
STM32F446ZEH7TR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your STM32F446ZEH7TR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for STM32F446ZEH7TR?
For technical support, including STM32F446ZEH7TR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your STM32F446ZEH7TR requirements.
6.How does Aetrix verify that STM32F446ZEH7TR is sourced from the original manufacturer or authorized distributors?
All STM32F446ZEH7TR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that STM32F446ZEH7TR meets industry standards.
7.What is the process for return or replacement of STM32F446ZEH7TR?
All STM32F446ZEH7TR units undergo pre-shipment inspection (PSI). If there is an issue with STM32F446ZEH7TR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The STM32F446ZEH7TR part is unused and in its original packaging.
Return procedure for STM32F446ZEH7TR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
STM32F446ZEH7TR Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

