STMicroelectronics STM32F765IGT6
- Part No.:
- STM32F765IGT6
- Manufacturer:
- STMicroelectronics
- Category:
- Microcontrollers
- Package:
- 176-LQFP
- Datasheet:
-
STM32F765IGT6.pdf
- Description:
- IC MCU 32BIT 1MB FLASH 176LQFP
- Quantity:
- Payment:

- Shipping:

Inventory:200
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
STM32F765IGT6 from STMicroelectronics is an Arm® Cortex®-M7 32-bit microcontroller with FPU, delivering 462 DMIPS at 216 MHz, featuring 2 MB dual-bank flash, 512 KB SRAM (including 128 KB data TCM), USB OTG HS/FS, MIPI DSI host controller, and LCD-TFT controller supporting XGA resolution. It serves as a high-performance application processor in industrial HMI, medical imaging front-ends, and embedded multimedia gateways.
For engineers reviewing the STM32F765IGT6 datasheet, STM32F765IGT6 pinout, STM32F765IGT6 application, or STM32F765IGT6 equivalent, key selection criteria include its dual-bank flash for safe firmware updates, hardware JPEG codec for real-time image compression, Chrom-ART Accelerator for low-CPU-load GUI rendering, and 3×12-bit 2.4 MSPS ADCs for sensor fusion in deterministic control loops.
Technical Context
The STM32F765IGT6 integrates a Cortex-M7 core with ART Accelerator and 16 KB I/D cache, enabling zero-wait-state execution from flash or external memory. Its AXI-AHB bus matrix supports concurrent access to flash, SRAM, and peripherals while maintaining deterministic latency for real-time tasks.
It implements three independent clock domains: AHB/APB for system/peripheral operation, dedicated audio/LCD PLLs (PLLI2S/PLLSAI) for jitter-sensitive interfaces, and MIPI D-PHY PLL for DSI video timing - all configurable via RCC registers without runtime penalty.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | Arm Cortex-M7 with FPU and DSP instructions, 462 DMIPS @ 216 MHz - enables floating-point-intensive motor control and audio processing without external coprocessor. |
| Flash Memory | 2 MB dual-bank flash with read-while-write capability - allows seamless over-the-air (OTA) firmware updates without halting application execution. |
| SRAM | 512 KB total: 128 KB data TCM + 16 KB instruction TCM + 4 KB backup SRAM - guarantees deterministic latency for time-critical ISR and real-time buffers. |
| Graphics Acceleration | Chrom-ART Accelerator (DMA2D) + hardware JPEG codec - offloads GUI composition and image decompression from CPU, reducing active power by up to 35% in HMI applications. |
| Display Interface | MIPI DSI host controller supporting 720p@30 Hz + LCD-TFT controller up to XGA (1024×768) - enables direct connection to high-resolution touch displays without external bridge ICs. |
| Analog Peripherals | 3×12-bit 2.4 MSPS ADCs (24 channels), 2×12-bit DACs, DFSDM (8 channels/4 filters) - supports simultaneous sampling of multi-axis sensors and sigma-delta current sensing in servo drives. |
| Connectivity | 3×CAN 2.0B, 10/100 Ethernet MAC with IEEE 1588v2, USB OTG HS/FS, SPDIFRX, HDMI-CEC - meets industrial networking and multimedia I/O requirements in single-chip edge nodes. |
Pinout & Package
LQFP100 (14 × 14 mm, 0.5 mm pitch) package with 100 pins, ECOPACK2 compliant. Pin count and signal assignment match ST's standardized LQFP100 footprint for STM32F7-series devices.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD, VDDA, VDDIO2 | Power supply inputs | Separate analog (VDDA), core (VDD), and I/O (VDDIO2) rails enable noise isolation for ADC and high-speed digital interfaces. |
| VCAP1, VCAP2 | Internal regulator decoupling | Two 2.2 µF ceramic capacitors required per pin to stabilize 1.2 V core voltage; omission causes boot failure or erratic FPU operation. |
| PA0–PA15, PB0–PB15, etc. | General-purpose I/O | Up to 166 5 V-tolerant pins support mixed-voltage system interfacing; most support multiple alternate functions including DSI, FMC, and SDMMC. |
| PH13–PH15, PI0–PI12 | MIPI DSI lane signals | Dedicated high-speed differential pairs (CLKP/N, D0P/N–D3P/N) routed on inner layers for EMI control; require controlled impedance (100 Ω differential). |
| PD0–PD15, PE0–PE15 | Flexible memory controller (FMC) | 32-bit data bus + address/control lines support NOR, PSRAM, SDRAM, and NAND - enables external frame buffer for full-screen GUI rendering. |
Key Features
| Feature | Design Value |
|---|---|
| ART Accelerator + L1 cache | Enables 0-wait-state execution from flash at 216 MHz, eliminating performance penalty of internal code storage vs. external RAM. |
| Dual-bank flash with RWW | Allows background firmware update in Bank 1 while executing from Bank 0 - critical for fail-safe OTA deployment in medical and industrial systems. |
| Chrom-ART Accelerator (DMA2D) | Performs 2D bitmap blending, rotation, and color format conversion in hardware - reduces GUI refresh CPU load from >40% to <5% in Qt-based HMIs. |
| Hardware JPEG codec | Compresses/decompresses 1024×768 RGB images in ≤12 ms - enables real-time thumbnail generation and camera feed preprocessing without software library overhead. |
| DFSDM with digital filtering | Processes 8 sigma-delta modulator streams simultaneously using 4 configurable filters - replaces external delta-sigma ADCs in precision current/voltage monitoring. |
Applications
| Industrial HMI Terminal | Medical Imaging Front-End |
|---|---|
Use Scenario: Touchscreen-based operator interface for PLC-controlled machinery with real-time alarm visualization and trend logging. IC Role / Device Role / Timing Role: Primary application MCU managing display refresh (via DSI), touch controller interface, CAN bus diagnostics, and local data buffering. Use Value: Chrom-ART and JPEG acceleration reduce GUI frame latency to <16 ms, meeting IEC 61508 SIL-2 response time requirements for safety-critical alerts. |
Use Scenario: Portable ultrasound device requiring real-time beamforming data preprocessing and grayscale image rendering on integrated display. IC Role / Device Role / Timing Role: Real-time signal processor handling ADC oversampling, FIR filtering, and DICOM-compliant JPEG compression before display. Use Value: Dual-bank flash enables field-upgradable image processing algorithms; hardware JPEG cuts compression latency from 85 ms to 11 ms at 1024×768 resolution. |
| Smart Building Gateway | Automated Test Equipment (ATE) |
Use Scenario: Edge gateway aggregating Modbus, BACnet MS/TP, and KNX data into MQTT payloads for cloud upload, with local web UI. IC Role / Device Role / Timing Role: Network protocol stack host with Ethernet MAC, multiple UARTs for legacy fieldbus bridging, and LCD for local configuration. Use Value: IEEE 1588v2 hardware timestamping ensures sub-microsecond synchronization across distributed HVAC controllers in time-sensitive commissioning workflows. |
Use Scenario: Modular ATE mainframe controlling precision DC sources, SMUs, and digitizers via PCIe-to-USB bridges and high-speed GPIO patterns. IC Role / Device Role / Timing Role: Timing and sequencing controller generating synchronized trigger pulses, reading calibration data from 24-channel ADCs, and managing USB OTG HS test data transfer. Use Value: 3×12-bit 2.4 MSPS ADCs capture transient waveforms at 100 ns intervals; DFSDM filters sigma-delta outputs from reference-grade SMUs with <0.001% THD. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar high-performance ARM Cortex-M7 MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| STM32F767IGT6 | Same core, flash, and RAM; adds Ethernet PHY and second USB OTG HS port - no DSI or LCD-TFT controller. | Better suited for network-centric gateways; lacks native display interface - requires external bridge IC for TFT panels. | Select when Ethernet and dual USB OTG are prioritized over integrated display control. |
| STM32H743VIT6 | Higher clock (480 MHz), dual-core (Cortex-M7 + M4), 2 MB flash, but no DSI host - uses parallel RGB or LVDS for display output. | Superior compute throughput for AI inference; display subsystem requires external timing controller or RGB interface routing complexity. | Choose for ML-edge inference workloads where display is secondary; avoid if DSI-native panel integration is mandatory. |
Compared with STM32F767IGT6, the STM32F765IGT6 trades Ethernet PHY and dual USB OTG for DSI/LCD-TFT - making it optimal for display-first designs. Versus STM32H743VIT6, it offers lower power and simpler layout for DSI-based HMIs but lacks dual-core flexibility for heterogeneous task partitioning.
Availability
STM32F765IGT6 is available at Aetrix Electronics and suitable for industrial HMI terminals, portable medical imaging devices, and smart building gateways requiring stable component supply, long-term lifecycle assurance, and ECOPACK2 compliance.
Supply support for STM32F765IGT6 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, specializing in microcontrollers, power management, and MEMS sensors for industrial, automotive, and consumer markets.
The STM32F7 series targets high-end embedded applications demanding real-time performance, rich graphics, and multi-protocol connectivity - designed specifically for resource-constrained edge devices needing desktop-class processing without OS overhead.
FAQ
What is the maximum operating frequency and how is it achieved?
The STM32F765IGT6 achieves 216 MHz maximum CPU frequency using the internal voltage regulator with VDD = 3.3 V and VCAP1/VCAP2 decoupling capacitors properly installed. This requires enabling the ART Accelerator and L1 cache; disabling either reduces effective throughput by ≥35%. The frequency is sustained across ambient temperatures from –40°C to +85°C per datasheet Section 6.3.1.
Does STM32F765IGT6 support secure boot and cryptographic acceleration?
Yes - it includes a True Random Number Generator (RNG), CRC calculation unit, and supports secure firmware installation via STM32CubeProgrammer with AES-128 encryption. However, it lacks dedicated cryptographic accelerators (AES, SHA, PKA) found in STM32L5 or H5 series; software libraries like mbed TLS are required for full TLS stack implementation.
Can the DSI interface drive a 1080p panel?
No - the DSI host controller is rated for up to 720p@30 Hz (1280×720) per Section 3.47 of DS11532 Rev 9. Driving 1080p requires external DSI-to-LVDS or DSI-to-eDP bridge ICs. For native high-resolution support, ST recommends STM32MP15x series with dual-display pipeline or STM32H753/757 with parallel RGB interface.
What debug interfaces are supported and what trace capability exists?
SWD and JTAG interfaces are supported, along with Cortex-M7 Trace Macrocell™ (ETM) for instruction-level tracing. Full ETM trace requires external debugger (e.g., ST-LINK/V3-SET) and 4-bit trace port; SWO is available for printf-style debugging over single-wire output. Trace depth is limited by external trace memory - not on-chip.
STM32F765IGT6 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Package/Case:
- 176-LQFP
- Series:
- STM32F7
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- ARM® Cortex®-M7
- Core Size:
- 32-Bit Single-Core
- Speed:
- 216MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, IrDA, LINbus, MMC/SD/SDIO, QSPI, SAI, SPDIF, SPI, UART/USART, USB OTG
- Peripherals:
- Brown-out Detect/Reset, DMA, I2S, POR, PWM, WDT
- Number of I/O:
- 140
- Program Memory Size:
- 1MB (1M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 512K x 8
- Voltage - Supply (Vcc/Vdd):
- 1.7V ~ 3.6V
- Data Converters:
- A/D 24x12b; D/A 2x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
STM32F765IGT6 FAQ
1.How can I place an order for STM32F765IGT6 through Aetrix?
Please submit a Request for Quotation (RFQ) for STM32F765IGT6 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for STM32F765IGT6 reliable?
The price and inventory of STM32F765IGT6 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for STM32F765IGT6 is usually 5 days.
3.What payment methods are accepted for STM32F765IGT6?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for STM32F765IGT6 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for STM32F765IGT6?
STM32F765IGT6 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your STM32F765IGT6 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for STM32F765IGT6?
For technical support, including STM32F765IGT6 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your STM32F765IGT6 requirements.
6.How does Aetrix verify that STM32F765IGT6 is sourced from the original manufacturer or authorized distributors?
All STM32F765IGT6 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that STM32F765IGT6 meets industry standards.
7.What is the process for return or replacement of STM32F765IGT6?
All STM32F765IGT6 units undergo pre-shipment inspection (PSI). If there is an issue with STM32F765IGT6, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The STM32F765IGT6 part is unused and in its original packaging.
Return procedure for STM32F765IGT6:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
STM32F765IGT6 Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

