STMicroelectronics STM32G071GBU3TR
- Part No.:
- STM32G071GBU3TR
- Manufacturer:
- STMicroelectronics
- Category:
- Microcontrollers
- Package:
- 28-UFQFN
- Datasheet:
-
STM32G071GBU3TR.pdf
- Description:
- IC MCU 32BIT 128KB FLSH 28UFQFPN
- Quantity:
- Payment:

- Shipping:

Inventory:3,555
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
STM32G071GBU3TR from STMicroelectronics is a 32-bit Arm® Cortex®-M0+ microcontroller in UFQFPN28 package, featuring 128 KB Flash, 36 KB SRAM, dual 12-bit DACs, 12-bit ADC (0.4 µs conversion), and operating voltage range of 1.7–3.6 V. It integrates USB Type-C Power Delivery controller, four USARTs (two with ISO7816/LIN/IrDA), two I²C interfaces (Fast-mode Plus), and RTC with alarm/wakeup-targeted for smart power adapters and embedded USB-C PD applications.
For engineers reviewing the STM32G071GBU3TR datasheet, STM32G071GBU3TR pinout, STM32G071GBU3TR application, or STM32G071GBU3TR equivalent, key selection criteria include its 28-pin UFQFPN footprint, 64 MHz max CPU frequency, dual DAC support for analog control loops, low-power timer capability (LPTIM1/LPTIM2), and integrated USB-C PD controller enabling single-chip PD policy engine implementation.
Technical Context
The STM32G071GBU3TR implements an Arm Cortex-M0+ core with MPU, supporting TrustZone-like memory protection via securable flash area and readout protection levels. Its clock system combines 4–48 MHz HSE, 32 kHz LSE with calibration, and ±1% internal 16 MHz HSI with PLL-enabling precise timing for USB-C PD negotiation and real-time motor control.
Analog subsystem includes two rail-to-rail 12-bit DACs with sample-and-hold, a 12-bit ADC with hardware oversampling up to 16-bit resolution, and two programmable comparators-configured for closed-loop voltage/current regulation in power delivery systems without external signal conditioning.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | Arm Cortex-M0+, 64 MHz max - enables deterministic real-time response for USB-C PD state machine execution. |
| Flash / RAM | 128 KB Flash (with securable area), 36 KB SRAM - sufficient for dual-role PD firmware + secure boot + application logic. |
| ADC | 12-bit, 0.4 µs conversion, up to 16 external channels - supports fast sampling of VBUS/VCONN/CC line voltages during PD contract negotiation. |
| DACs | Two 12-bit DACs with low-power sample-and-hold - used for precision reference generation in analog feedback paths for buck/boost controllers. |
| Timers | 14 timers including two 128 MHz-capable advanced timers and two low-power LPTIMs - enables high-resolution PWM for power stage control and ultra-low-power wake-up timing. |
| I/O Voltage Tolerance | Multiple 5 V-tolerant pins - allows direct interfacing with legacy 5 V logic or CC line signaling without level shifters. |
| USB-C PD Controller | Integrated USB Type-C Power Delivery controller - handles BMC decoding/encoding, PD message parsing, and policy engine execution without external IC. |
Pinout & Package
STM32G071GBU3TR is housed in a 28-pin Ultra-Fine Pitch Quad Flat No-lead (UFQFPN28) package, 4.0 × 4.0 mm, 0.5 mm pitch, with exposed thermal pad. Pin mapping follows ST's standard UFQFPN28 layout per DS12232 Rev 5 Section 4 (Pinouts, pin description and alternate functions).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD, VSS | Power supply and ground | Dual VDD/VSS pairs ensure stable core/peripheral rail decoupling; VDDA separate for analog domain integrity. |
| PA0–PA15, PB0–PB15, PC13–PC15, PF0–PF1 | General-purpose I/O | Up to 60 fast I/Os; multiple 5 V-tolerant pins (e.g., PA9, PA10) directly interface with USB-C CC lines and VCONN switches. |
| PA2/PA3, PA9/PA10 | USART1/USART2 TX/RX | Support ISO7816, LIN, IrDA, auto-baud detection - used for PD communication over CC lines and debug console. |
| PA4–PA7 | ADC1_IN0–IN3 | Direct connection to internal ADC channels - monitors VBUS, battery voltage, current sense amplifier outputs. |
| PA4, PA5 | DAC1_OUT, DAC2_OUT | Output analog references for voltage/current regulation loops - sample-and-hold maintains stability during PWM dead-time. |
| PA1, PA4 | COMP1_INP, COMP2_INP | Rail-to-rail comparators with programmable hysteresis - implement fast overvoltage/overcurrent trip detection independent of CPU. |
| PD0, PD1 | USB-C CC1/CC2 | Dedicated USB-C configuration channel pins - internally routed to PD controller for BMC signaling and plug orientation detection. |
| VBAT | Backup power supply | Supplies RTC and backup registers during main power loss - critical for maintaining PD session state across adapter power cycles. |
Key Features
| Feature | Design Value |
|---|---|
| Integrated USB-C PD controller | Eliminates need for external PD PHY/controller IC, reducing BOM count and PCB area in compact AC/DC adapters. |
| Securable flash area with ROP | Enables firmware IP protection and secure bootloader execution - required for certified USB-IF PD implementations. |
| Low-power modes (Stop/Standby/Shutdown) | Sub-µA shutdown current with VBAT retention - extends battery life in portable PD sink devices like power banks. |
| Hardware CRC calculation unit | Accelerates PD message integrity checks and firmware update validation - improves security and reduces CPU load. |
| 96-bit unique ID | Provides device-specific identity for PD port enumeration and secure provisioning in multi-port hubs. |
Applications
| USB-C Power Adapter | Smart Charging Hub |
|---|---|
Use Scenario: Compact 20–65 W GaN-based AC/DC adapter negotiating variable voltage profiles (5–20 V) with laptops and tablets. IC Role / Device Role / Timing Role: Primary PD policy engine and power stage controller - manages CC line BMC signaling, voltage rail sequencing, and real-time current limiting. Use Value: Integrated PD controller + dual DACs + fast ADC enable single-chip solution with <10 ms PD contract negotiation and <50 µs overcurrent response. | Use Scenario: Multi-port desktop hub delivering simultaneous 60 W (laptop) + 18 W (phone) + 5 V USB data ports. IC Role / Device Role / Timing Role: Central PD resource manager coordinating power allocation across ports using dynamic PDO selection and thermal derating logic. Use Value: 36 KB SRAM supports concurrent PD stack instances; LPTIM2 enables precise 100 ms thermal sampling intervals without waking CPU. |
| Programmable Power Supply | USB-C Monitor Power Delivery |
Use Scenario: Lab-grade bench PSU with programmable voltage/current limits and USB-C PD compliance testing mode. IC Role / Device Role / Timing Role: Precision analog front-end controller - digitizes setpoint inputs, generates reference DAC outputs, and validates PD messages via hardware BMC engine. Use Value: 12-bit DACs with sample-and-hold deliver <0.1% output stability; 12-bit ADC achieves 16-bit effective resolution via oversampling for accurate current sensing. | Use Scenario: Display with USB-C upstream port providing 15 W power to connected laptop while receiving video/data. IC Role / Device Role / Timing Role: Sink-side PD controller managing VBUS negotiation, cable discovery, and fault recovery (e.g., VBUS disconnect/reconnect). Use Value: Dual comparators monitor CC line states independently; RTC alarm wakes CPU from Stop mode within 2 µs to handle hot-plug events. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar USB-C PD controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| STM32G071CBT6 | LQFP48 package (48 pins), same core/peripherals but larger footprint and higher I/O count | Better suited for designs requiring >28 GPIOs or additional SPI/I²C buses beyond GBU3TR's UFQFPN28 routing constraints | Select when board space allows larger package and extra peripherals (e.g., second ADC, more timers) are needed. |
| STM32G0B1CBT6 | Higher Flash (128 KB) and RAM (144 KB), enhanced USB-C PD features including extended message buffer and faster BMC timing | Targeted at USB-IF certified 100 W+ PD3.0 EPR applications requiring extended power range and fast role swap | Choose for next-gen PD3.1/EPR compliance where G071GBU3TR lacks extended message handling and Vconn switching control. |
Compared with STM32G071CBT6, the GBU3TR offers superior space efficiency and lower thermal density in compact adapters; versus STM32G0B1CBT6, it provides cost-optimized PD2.0 compliance without EPR overhead-ideal for mainstream 65 W adapters requiring rapid time-to-market.
Availability
STM32G071GBU3TR is available at Aetrix Electronics and suitable for USB-C power adapters, smart charging hubs, programmable lab PSUs, and display-integrated PD sinks requiring stable component supply and long-term industrial availability.
Supply support for STM32G071GBU3TR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, specializing in microcontrollers, power management, and automotive ICs with strong focus on energy-efficient embedded solutions.
The STM32G0 series targets cost-sensitive, ultra-low-power applications demanding USB-C PD integration, secure firmware execution, and compact form factors-designed specifically for smart power delivery and IoT edge nodes.
FAQ
What is the maximum operating temperature rating for STM32G071GBU3TR?
The STM32G071GBU3TR is qualified for operation from –40°C to 125°C ambient temperature, meeting industrial-grade reliability requirements. This rating is validated per ST's production test flow and applies to all package variants including UFQFPN28. Thermal performance is supported by the exposed thermal pad and specified junction-to-ambient thermal resistance (θJA = 150°C/W) in DS12232 Rev 5 Section 6.3.
Does STM32G071GBU3TR support USB-C Power Delivery 3.0 or Extended Power Range (EPR)?
No, STM32G071GBU3TR implements USB-C PD specification version 2.0 only. It supports fixed and programmable PDOs up to 20 V/5 A (100 W), but lacks hardware support for EPR voltage ranges (28–48 V), fast role swap (FRS), or extended message buffers required for PD3.0/EPR certification. For EPR, ST recommends STM32G0B1 or STM32G4 series.
How many USB-C configuration channel (CC) pins are physically available on the UFQFPN28 package?
The STM32G071GBU3TR in UFQFPN28 exposes two dedicated CC pins: PD0 (CC1) and PD1 (CC2), both internally connected to the USB-C PD controller's BMC transceiver. These pins support plug orientation detection, VCONN source switching, and full BMC signaling per USB-C specification-no external transceivers or level shifters are required for basic PD2.0 operation.
Can the internal 12-bit DACs operate during Stop mode?
No, the DACs are disabled in Stop mode. However, the STM32G071GBU3TR supports DAC output retention in Standby mode when VDD is maintained and the DAC trigger is configured for EXTI wakeup. In Stop mode, only LSE, RTC, and backup registers remain active; analog peripherals including DAC, ADC, and comparators are powered down to achieve sub-1 µA current consumption.
STM32G071GBU3TR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Package/Case:
- 28-UFQFN
- Series:
- STM32G0
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- ARM® Cortex®-M0+
- Core Size:
- 32-Bit Single-Core
- Speed:
- 64MHz
- Connectivity:
- HDMI-CEC, I2C, IrDA, LINbus, SPI, UART/USART, USB Type-C™ (Power Delivery)
- Peripherals:
- Brown-out Detect/Reset, DMA, I2S, POR, PWM, Temp Sensor, WDT
- Number of I/O:
- 26
- Program Memory Size:
- 128KB (128K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 36K x 8
- Voltage - Supply (Vcc/Vdd):
- 1.7V ~ 3.6V
- Data Converters:
- A/D 12x12b; D/A 2x12b
- Oscillator Type:
- External, Internal
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
STM32G071GBU3TR FAQ
1.How can I place an order for STM32G071GBU3TR through Aetrix?
Please submit a Request for Quotation (RFQ) for STM32G071GBU3TR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for STM32G071GBU3TR reliable?
The price and inventory of STM32G071GBU3TR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for STM32G071GBU3TR is usually 5 days.
3.What payment methods are accepted for STM32G071GBU3TR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for STM32G071GBU3TR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for STM32G071GBU3TR?
STM32G071GBU3TR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your STM32G071GBU3TR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for STM32G071GBU3TR?
For technical support, including STM32G071GBU3TR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your STM32G071GBU3TR requirements.
6.How does Aetrix verify that STM32G071GBU3TR is sourced from the original manufacturer or authorized distributors?
All STM32G071GBU3TR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that STM32G071GBU3TR meets industry standards.
7.What is the process for return or replacement of STM32G071GBU3TR?
All STM32G071GBU3TR units undergo pre-shipment inspection (PSI). If there is an issue with STM32G071GBU3TR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The STM32G071GBU3TR part is unused and in its original packaging.
Return procedure for STM32G071GBU3TR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
STM32G071GBU3TR Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

