STMicroelectronics STM32G0B0VET6TR
- Part No.:
- STM32G0B0VET6TR
- Manufacturer:
- STMicroelectronics
- Category:
- Microcontrollers
- Package:
- 100-LQFP
- Datasheet:
-
STM32G0B0VET6TR.pdf
- Description:
- IC MCU 32BIT 512KB FLASH 100LQFP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
STM32G0B0VET6TR from STMicroelectronics is an Arm® Cortex®-M0+ 32-bit microcontroller with 512 KB flash, 144 KB SRAM, six USARTs, USB 2.0 FS host/device interface, and operation from 2.0–3.6 V. It integrates a 12-bit ADC (0.4 µs conversion), 12 timers including advanced motor control TIM1, RTC with alarm, and up to 93 5 V-tolerant I/Os-deployed in industrial HMI, smart metering, and battery-powered sensor nodes.
For engineers reviewing the STM32G0B0VET6TR datasheet, STM32G0B0VET6TR pinout, STM32G0B0VET6TR application, or STM32G0B0VET6TR equivalent, key selection criteria include dual-bank flash with read-while-write, hardware parity on 128 KB SRAM, USB FS device/host capability, 32 kHz crystal oscillator with calibration, and support for Stop/Standby wakeup via multiple peripherals including I²C, USART, and RTC alarms.
Technical Context
The STM32G0B0VET6TR implements an Arm Cortex-M0+ core with MPU, executing at up to 64 MHz with 1.25 DMIPS/MHz efficiency. Its memory subsystem features dual-bank flash enabling seamless firmware updates and 144 KB SRAM (128 KB with hardware parity), supporting robust real-time data buffering and error detection.
Clock architecture includes four independent sources: 4–48 MHz HSE, 32.768 kHz LSE with ±20 ppm calibration, 16 MHz HSI with ±1% accuracy, and 32 kHz LSI (±5%). These feed a flexible clock tree with PLL (×2–×32), enabling precise timing for USB, ADC sampling, and communication interfaces.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Core | Arm Cortex-M0+, 64 MHz max - delivers deterministic real-time execution with low interrupt latency for control-loop applications. |
| Flash Memory | 512 KB, dual-bank, read-while-write - enables over-the-air (OTA) firmware updates without halting application code. |
| SRAM | 144 KB total; 128 KB with hardware parity - ensures data integrity in safety-critical buffer storage and stack operations. |
| ADC | 12-bit, 0.4 µs conversion time, up to 16 external channels - supports high-speed analog sensing with hardware oversampling up to 16-bit effective resolution. |
| Communication Interfaces | 6 × USART (3 with ISO7816/LIN/IrDA), 3 × I²C (Fast-mode Plus, 1 Mbit/s), 3 × SPI (32 Mbit/s), USB 2.0 FS host/device - provides multi-protocol connectivity for industrial gateways and peripheral bridging. |
| Timers | 12 timers: 1 × advanced-control (TIM1), 6 × general-purpose, 2 × basic, 2 × watchdogs, SysTick - enables motor FOC, PWM generation, pulse counting, and system supervision. |
| Operating Voltage | 2.0–3.6 V - compatible with single-cell Li-ion, 3.3 V logic rails, and wide-input DC-DC converters in portable and embedded systems. |
| Temperature Range | −40°C to +85°C - qualified for industrial ambient environments without derating. |
Pinout & Package
LQFP100 package (14 × 14 mm, 0.5 mm pitch), ECOPACK2-compliant, with 100 pins including 93 fast I/Os (multiple 5 V-tolerant), VDD/VSS power pairs, dedicated USB DP/DM, crystal inputs (HSE/LSE), and SWD debug pins (SWCLK/SWDIO).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD, VDDA, VDDIO2 | Power supply inputs | Separate domains for digital core, analog, and I/O banks enable noise isolation and flexible rail sequencing. |
| VSS, VSSA, VSSIO2 | Ground returns | Dedicated analog and I/O ground planes reduce coupling noise into ADC and high-speed digital signals. |
| PA13/SWDIO, PA14/SWCLK | Debug interface | Serial Wire Debug (SWD) pins support non-intrusive programming and real-time trace without dedicated JTAG pins. |
| PA11/USB_DM, PA12/USB_DP | USB physical layer | Integrated USB transceiver with internal pull-ups eliminates need for external resistors in device mode. |
| PC13/LSE_IN, PC14/LSE_OUT | Low-speed crystal oscillator | 32.768 kHz crystal connection with factory-calibrated trimming for accurate RTC timekeeping and low-power wakeup. |
| PF0/OSC_IN, PF1/OSC_OUT | High-speed crystal oscillator | 4–48 MHz crystal input supports USB timing, high-resolution PWM, and fast serial communication. |
Key Features
| Feature | Design Value |
|---|---|
| Dual-bank flash with RWW | Enables zero-downtime firmware updates by executing from one bank while erasing/writing the other. |
| Hardware CRC calculation unit | Accelerates checksum computation for firmware validation and communication packet integrity (e.g., Modbus, CAN FD frames). |
| 12-channel DMA with flexible mapping | Offloads CPU from memory transfers across peripherals (ADC→SRAM, USART→buffer), reducing ISR overhead and jitter. |
| Calendar RTC with tamper detection | Provides timestamped event logging and secure boot enforcement via backup domain registers powered by VBAT. |
| USB 2.0 FS host/device controller | Supports CDC, HID, and MSC class devices without external PHY-reducing BOM cost and PCB area in field-service tools. |
| Multiple low-power modes | Stop 0 (1.1 µA), Standby (0.4 µA), and VBAT mode (0.3 µA) extend battery life in always-on sensor endpoints and metering applications. |
Applications
| Industrial HMI Panel | Smart Electricity Meter |
|---|---|
|
Use Scenario: Touch-enabled local display with button inputs, RS-485 communication, and energy measurement logging. IC Role / Device Role / Timing Role: Main application controller managing GUI rendering, UART-based meter reading, and RTC-synchronized data storage. Use Value: Dual-bank flash allows remote firmware upgrades during off-peak hours; 12-bit ADC interfaces directly to shunt-based current sensing with hardware oversampling. |
Use Scenario: DIN-rail mounted meter with metrology IC interface, PLC communication, and tamper-proof event logging. IC Role / Device Role / Timing Role: System manager coordinating metrology data acquisition, secure storage in backup registers, and IR/RS-485 data transmission. Use Value: RTC with tamper detection triggers secure erase of sensitive registers upon enclosure breach; VBAT-backed registers retain configuration during main power loss. |
| Battery-Powered Sensor Node | Motor Control Gateway |
|
Use Scenario: LoRaWAN edge node monitoring temperature, humidity, and vibration using MEMS sensors and BLE/USB provisioning. IC Role / Device Role / Timing Role: Central MCU handling sensor fusion, low-power scheduling, and USB-CDC virtual COM port for field configuration. Use Value: Stop 0 mode (1.1 µA) with RTC wakeup enables hourly sensor reads; USB FS device mode simplifies firmware updates via standard PC tools. |
Use Scenario: Brushless DC motor drive with Hall-effect feedback, current sensing, and CAN bus telemetry reporting. IC Role / Device Role / Timing Role: Real-time motion controller generating 6-channel complementary PWM with dead-time insertion and fault shutdown. Use Value: TIM1 advanced timer supports center-aligned PWM and synchronous ADC triggering for precise current loop sampling; 5 V-tolerant GPIOs interface directly to Hall sensors. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| STM32G0B1VET6 | Same core, flash, RAM, and peripherals-but lacks USB host capability and has no hardware crypto acceleration. | Suitable for pure device-only USB or cost-sensitive designs where host functionality is unnecessary. | Select when USB host is not required and lower BOM cost is prioritized over full USB dual-role flexibility. |
| STM32G431VBT6 | Higher-performance Cortex-M4F (170 MHz), FPU, 128 KB flash, 32 KB SRAM, no USB host, but adds analog comparator and op-amps. | Better suited for math-intensive control (e.g., PMSM FOC) but lacks integrated USB host and has smaller memory. | Choose for analog-rich, compute-heavy motor control where USB host is secondary and floating-point performance is critical. |
Compared with STM32G0B1VET6, the STM32G0B0VET6TR adds USB host functionality and enhanced security features; versus STM32G431VBT6, it trades FPU and analog peripherals for larger memory and full USB dual-role support-making it optimal for connected, update-capable industrial endpoints.
Availability
STM32G0B0VET6TR is available at Aetrix Electronics and suitable for industrial HMI, smart metering, battery-powered sensor nodes, and motor control gateways requiring stable component supply across multi-year production cycles.
Supply support for STM32G0B0VET6TR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power management ICs, sensors, and automotive semiconductors.
The STM32G0 series targets cost-sensitive, power-efficient, and secure entry-level embedded applications-emphasizing simplified development, robust security primitives, and seamless integration into industrial and consumer IoT systems.
FAQ
What is the maximum operating frequency and core type of the STM32G0B0VET6TR?
The STM32G0B0VET6TR uses an Arm Cortex-M0+ core rated for up to 64 MHz operation, delivering 1.25 DMIPS/MHz. It achieves this frequency using the internal 16 MHz HSI oscillator with PLL multiplication or an external 4–48 MHz crystal. The core includes a Memory Protection Unit (MPU) and supports Thumb-2 instruction set for compact, efficient code execution in resource-constrained environments.
Does the STM32G0B0VET6TR support USB host functionality, and what interfaces does it require?
Yes, the STM32G0B0VET6TR integrates a full-speed USB 2.0 host/device controller compliant with USB Specification Revision 2.0. It requires only the PA11 (DM) and PA12 (DP) pins plus a 1.5 kΩ pull-up resistor on DP for device mode or external VBUS sensing circuitry for host mode. No external PHY is needed, and the controller supports CDC, HID, and MSC classes natively via ST's USB device library.
How many I/O pins are 5 V-tolerant, and which packages support them?
The STM32G0B0VET6TR supports up to 93 fast I/Os, with multiple pins designated as 5 V-tolerant-including all pins in groups PA, PB, PC, PD, PE, and PF except those dedicated to USB, crystal, or analog functions. This tolerance applies specifically to the LQFP100 package (VET6 suffix), confirmed in Section 5.3.14 of DS13565 Rev 3. Tolerance is not guaranteed in smaller packages like LQFP64 or LQFP48 for this part number variant.
What low-power modes are available, and what is the lowest achievable current draw?
The STM32G0B0VET6TR offers Sleep, Stop 0, Stop 1, Standby, and VBAT modes. In Standby mode with RTC and backup registers active, typical current consumption is 0.4 µA at 25°C; in VBAT mode (RTC + backup SRAM only), it drops to 0.3 µA. Wakeup is supported from all modes via EXTI lines, RTC alarm, I²C address match, or USART start-bit detection-enabling responsive, ultra-low-power sensor polling.
STM32G0B0VET6TR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Package/Case:
- 100-LQFP
- Series:
- STM32G0
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- ARM® Cortex®-M0+
- Core Size:
- 32-Bit
- Speed:
- 64MHz
- Connectivity:
- I2C, IrDA, LINbus, SPI, UART/USART, USB
- Peripherals:
- DMA, I2S, POR, PWM, Voltage Detect, WDT
- Number of I/O:
- 93
- Program Memory Size:
- 512KB (512K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 144K x 8
- Voltage - Supply (Vcc/Vdd):
- 2V ~ 3.6V
- Data Converters:
- A/D 19x12b SAR
- Oscillator Type:
- External, Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
STM32G0B0VET6TR FAQ
1.How can I place an order for STM32G0B0VET6TR through Aetrix?
Please submit a Request for Quotation (RFQ) for STM32G0B0VET6TR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for STM32G0B0VET6TR reliable?
The price and inventory of STM32G0B0VET6TR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for STM32G0B0VET6TR is usually 5 days.
3.What payment methods are accepted for STM32G0B0VET6TR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for STM32G0B0VET6TR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for STM32G0B0VET6TR?
STM32G0B0VET6TR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your STM32G0B0VET6TR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for STM32G0B0VET6TR?
For technical support, including STM32G0B0VET6TR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your STM32G0B0VET6TR requirements.
6.How does Aetrix verify that STM32G0B0VET6TR is sourced from the original manufacturer or authorized distributors?
All STM32G0B0VET6TR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that STM32G0B0VET6TR meets industry standards.
7.What is the process for return or replacement of STM32G0B0VET6TR?
All STM32G0B0VET6TR units undergo pre-shipment inspection (PSI). If there is an issue with STM32G0B0VET6TR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The STM32G0B0VET6TR part is unused and in its original packaging.
Return procedure for STM32G0B0VET6TR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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