My Inquiry
My Account
STMicroelectronics STM32H503CBU7
- Part No.:
- STM32H503CBU7
- Manufacturer:
- STMicroelectronics
- Category:
- Microcontrollers
- Package:
- 48-UFQFN Exposed Pad
- Datasheet:
-
STM32H503CBU7.pdf
- Description:
- STM32H503CBU7
- Quantity:
- Payment:
- Shipping:
Inventory:3,599
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
STM32H503CBU7 from STMicroelectronics is an Arm® Cortex®-M33 32-bit microcontroller with FPU, operating up to 250 MHz (375 DMIPS), featuring 128 Kbytes flash memory with ECC, 32 Kbytes SRAM with ECC, and integrated I3C, FDCAN, USB 2.0 FS host/device, and hardware security accelerators (HASH, RNG, 96-bit UID). It targets secure, low-power industrial control and IoT edge nodes requiring real-time performance and cryptographic integrity.
For engineers reviewing the STM32H503CBU7 datasheet, STM32H503CBU7 pinout, STM32H503CBU7 application, or STM32H503CBU7 equivalent, key selection criteria include its dual-bank read-while-write flash, 2.5 MSPS 12-bit ADC, ultra-low-power comparator, 7 MHz op-amp, and support for Stop/Standby modes with VBAT-backed RTC and 32 backup registers.
Technical Context
The device implements a TrustZone-enabled Arm Cortex-M33 core with Memory Protection Unit (MPU) and optional secure firmware execution. Its ART Accelerator includes an 8-Kbyte 2-way set-associative instruction cache enabling zero-wait-state execution at 250 MHz from flash.
Power management integrates dual PLLs (system/USB/audio/ADC), embedded LDO regulator, POR/PDR/PVD/BOR, and three low-power modes (Sleep, Stop, Standby) with wake-up via fast I/Os (up to 49, most 5 V tolerant) or RTC alarm. Analog subsystem includes one 12-bit dual-channel DAC, digital temperature sensor, and operational amplifier with 7 MHz bandwidth.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | Arm Cortex-M33 with FPU, MPU, DSP instructions - enables secure real-time control with floating-point math and memory isolation. |
| Max Clock Frequency | 250 MHz - delivers 375 DMIPS and 1023 CoreMark®, supporting demanding signal processing in compact footprint. |
| Flash Memory | 128 Kbytes with ECC and dual-bank RWW - allows safe over-the-air firmware updates without halting execution. |
| SRAM | 32 Kbytes with ECC + 2 Kbytes backup SRAM - ensures data integrity during operation and retention in lowest power modes. |
| Analog Peripherals | 12-bit ADC (2.5 MSPS), dual-channel 12-bit DAC, ultra-low-power comparator, 7 MHz op-amp - supports precision sensor interfacing and closed-loop control. |
| Security Features | HASH (SHA-1/SHA-2), HMAC, true random number generator, 96-bit unique ID, active tamper detection - meets IEC 62443-3-3 SL2 requirements for secure boot and runtime attestation. |
| Communication Interfaces | Up to 2× I3C (shared with I2C), 3× USART/LPUART, 3× SPI/I2S, FDCAN, USB 2.0 FS host/device - enables mixed-protocol industrial connectivity with time-critical CAN FD messaging. |
Pinout & Package
STM32H503CBU7 is packaged in UFQFPN32 (5 × 5 mm, 0.5 mm pitch), a space-constrained, thermally efficient package suitable for high-density PCB layouts. Pin functions are validated per STMicroelectronics DS14053 Rev 4, Section 4.2.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD, VSS | Core power supply and ground | 1.71–3.6 V main supply; decoupling required per datasheet layout guidelines for stable 250 MHz operation. |
| VCAP | Internal LDO output capacitor connection | External 2.2 µF ceramic capacitor stabilizes core voltage rail; mandatory for reliable high-frequency operation. |
| NRST | Active-low reset input | Asynchronous reset with internal pull-up; accepts external push-button or supervisor IC assertion for system recovery. |
| PA0–PA15, PB0–PB15, PC0–PC15, PD0–PD15, PE0–PE15 | General-purpose I/Os | Up to 49 fast GPIOs with interrupt capability; most tolerate 5 V inputs - simplifies level-shifting in mixed-voltage systems. |
| PA1, PA4, PA5, PA6, PA7, PB0, PB1, PB10, PB11 | Analog input channels | ADC1 IN0–IN9 and DAC1/2 outputs - supports simultaneous sampling and analog waveform generation with hardware synchronization. |
| PA9, PA10, PA11, PA12, PB14, PB15 | USB D+/D−, DP/DM | Dedicated full-speed USB 2.0 transceiver pins - enables plug-and-play device/host functionality without external PHY. |
| PA13, PA14, PA15 | SWDIO, SWCLK, NRST | Serial Wire Debug interface - provides non-intrusive debug access with minimal pin count and no JTAG TCK/TMS overhead. |
Key Features
| Feature | Design Value |
|---|---|
| ART Accelerator with 8-Kbyte ICACHE | Enables zero-wait-state 250 MHz execution from flash, eliminating SRAM code shadowing and reducing BOM cost. |
| Dual-bank flash with RWW | Allows background firmware update while executing from alternate bank - critical for fail-safe OTA deployment in fielded devices. |
| Hardware crypto acceleration (HASH/RNG) | Offloads SHA-256 and random number generation from CPU, reducing latency and power vs. software-only implementations. |
| Ultra-low-power analog block | Comparator and op-amp operate in Stop mode with sub-µA quiescent current - enables always-on sensor wake-up without MCU core activation. |
| I3C interface compliant with MIPI v1.1 | Provides higher bandwidth and lower pin count than I2C, with dynamic address assignment and in-band interrupt support for smart sensor hubs. |
Applications
| Industrial PLC I/O Module | Secure Edge Gateway |
|---|---|
Use Scenario: Compact programmable logic controller module collecting analog sensor data (temperature, pressure) and driving discrete actuators via isolated outputs. IC Role / Device Role / Timing Role: Main controller executing real-time ladder logic, managing ADC sampling at 2.5 MSPS, generating PWM via advanced timers, and communicating via FDCAN to fieldbus networks. Use Value: Dual-bank flash enables safe firmware updates during runtime; 32 Kbytes ECC SRAM ensures deterministic response under EMI stress; 5 V-tolerant GPIOs simplify interface to legacy 24 V industrial sensors. | Use Scenario: Battery-powered wireless gateway aggregating BLE/Zigbee sensor data and forwarding encrypted payloads to cloud via cellular or Ethernet. IC Role / Device Role / Timing Role: Secure application processor handling TLS handshake acceleration via HASH/RNG, managing low-power LPUART/I3C peripheral bridges, and maintaining RTC calendar in Standby mode. Use Value: Hardware RNG and SHA-256 accelerate TLS 1.3 handshakes by >5× vs. software; VBAT-backed 32-register backup retains session keys across power cycles; Stop mode current <1.5 µA extends battery life. |
| Smart Energy Meter | Medical Wearable Sensor Hub |
Use Scenario: DIN-rail mounted electricity meter performing Class 0.2 accuracy metrology, tamper detection, and HPLC communication over powerline. IC Role / Device Role / Timing Role: Metrology co-processor interfacing with external sigma-delta ADC, executing anti-tamper algorithms using active tamper pins, and running HPLC PHY via USART with precise timing calibration. Use Value: Digital temperature sensor compensates ADC gain drift; active tamper detection triggers immediate flash erase on enclosure breach; hardware CRC validates firmware integrity before boot. | Use Scenario: Ultra-low-power wearable patch monitoring ECG, skin temperature, and motion via integrated analog front-end and inertial sensors. IC Role / Device Role / Timing Role: Sensor fusion hub acquiring analog ECG signals via op-amp/ADC chain, digitizing motion data via I3C-connected IMU, and transmitting compressed biosignals via LPUART to smartphone. Use Value: 7 MHz op-amp configures as high-gain instrumentation amplifier for microvolt-level ECG; digital temperature sensor enables real-time thermal compensation of analog path; Stop mode wake-up latency <3.5 µs captures transient arrhythmia events. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| STM32H563VIT6 | Higher flash (2 Mbytes), larger LQFP100 package, includes Ethernet MAC and OctoSPI - no I3C support. | Suitable for gateway-class applications requiring network stack offload and external XIP flash, not space-constrained edge nodes. | Select when needing >128 KB flash, Ethernet, or OctoSPI; avoid if I3C or UFQFPN32 footprint is mandatory. |
| STM32U575ZIT6 | Lower max frequency (160 MHz), no FDCAN or USB device mode, includes AES-256 but lacks I3C and dual-bank RWW flash. | Better suited for ultra-low-power sensor nodes where cryptographic throughput >100 Mbps is unnecessary and CAN bus is absent. | Choose for sub-1 µA Standby current and PSA Certified Level 3, but only if I3C, FDCAN, and 250 MHz performance are non-critical. |
Compared with STM32H563VIT6 and STM32U575ZIT6, the STM32H503CBU7 uniquely balances 250 MHz performance, I3C+ FDCAN connectivity, dual-bank RWW flash, and UFQFPN32 packaging - making it optimal for cost-sensitive, space-constrained industrial edge controllers requiring secure, real-time protocol convergence.
Availability
STM32H503CBU7 is available at Aetrix Electronics and suitable for industrial PLC modules, secure edge gateways, smart energy meters, and medical wearable sensor hubs requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.
Supply support for STM32H503CBU7 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power management ICs, MEMS, and automotive semiconductors since 1987.
The STM32H5 series targets high-security, high-performance edge computing with TrustZone, cryptographic accelerators, and advanced analog integration - specifically engineered for industrial automation, smart infrastructure, and certified medical devices.
FAQ
What is the maximum operating frequency and associated DMIPS rating?
The STM32H503CBU7 operates at up to 250 MHz with an Arm Cortex-M33 core and FPU, achieving 375 DMIPS (Dhrystone 2.1) and 1023 CoreMark®. This performance is sustained with ART Accelerator's 8-Kbyte instruction cache enabled, allowing zero-wait-state execution from flash memory.
Does this MCU support secure boot and runtime firmware validation?
Yes. The STM32H503CBU7 includes hardware-based secure boot via immutable ROM bootloader with public-key verification, plus HASH (SHA-256) and true RNG accelerators for firmware signature validation and secure key generation. Active tamper detection erases sensitive data upon physical intrusion.
What low-power modes are available and what peripherals remain active in each?
Three low-power modes are supported: Sleep (CPU stopped, peripherals active), Stop (1.5 µA typical, RTC, backup SRAM, IWDG, and selected I/Os active), and Standby (0.25 µA typical, RTC and 32 backup registers retained via VBAT). LPTIM and ultra-low-power comparator operate in Stop mode for event-driven wake-up.
Is the UFQFPN32 package pin-compatible with other STM32H5 variants?
No. The STM32H503CBU7 in UFQFPN32 (A0B8) has a unique 32-pin ballout optimized for its peripheral set and memory size. Pin compatibility exists only within same package option (e.g., STM32H503RBT6 in LQFP64 shares pinout with other LQFP64 H503 variants), not across package types.
STM32H503CBU7 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Package/Case:
- 48-UFQFN Exposed Pad
- Series:
- STM32H5
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- ARM® Cortex®-M33F
- Core Size:
- 32-Bit
- Speed:
- 250MHz
- Connectivity:
- CANbus, FIFO, I2C, IrDA, LINbus, SCI, SDIO, SMBus, SPI, UART/USART, USB
- Peripherals:
- Brown-out Detect/Reset, DMA, I2S, PDR, POR, PWM, SHA, TRNG, Voltage Detect, WDT
- Number of I/O:
- 35
- Program Memory Size:
- 128KB (128K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 32K x 8
- Voltage - Supply (Vcc/Vdd):
- 1.71V ~ 3.6V
- Data Converters:
- A/D 10x12b SAR; D/A 1x12b
- Oscillator Type:
- External, Internal
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
STM32H503CBU7 FAQ
1.How can I place an order for STM32H503CBU7 through Aetrix?
Please submit a Request for Quotation (RFQ) for STM32H503CBU7 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for STM32H503CBU7 reliable?
The price and inventory of STM32H503CBU7 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for STM32H503CBU7 is usually 5 days.
3.What payment methods are accepted for STM32H503CBU7?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for STM32H503CBU7 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for STM32H503CBU7?
STM32H503CBU7 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your STM32H503CBU7 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for STM32H503CBU7?
For technical support, including STM32H503CBU7 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your STM32H503CBU7 requirements.
6.How does Aetrix verify that STM32H503CBU7 is sourced from the original manufacturer or authorized distributors?
All STM32H503CBU7 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that STM32H503CBU7 meets industry standards.
7.What is the process for return or replacement of STM32H503CBU7?
All STM32H503CBU7 units undergo pre-shipment inspection (PSI). If there is an issue with STM32H503CBU7, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The STM32H503CBU7 part is unused and in its original packaging.
Return procedure for STM32H503CBU7:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
STM32H503CBU7 Tags
-
ATTINY4-TSHR
Microchip Technology
-
ATTINY10-TSHR
Microchip Technology
-
ATTINY10-TS8R
Microchip Technology
-
ATTINY202-SSNR
Microchip Technology
-
ATTINY202-SSFR
Microchip Technology
-
ATTINY402-SSNR
Microchip Technology
-
PIC16F15213T-I/MF
Microchip Technology
-
PIC16F15213-E/MF
Microchip Technology
-
PIC10F200T-I/OT
Microchip Technology
-
ATTINY412-SSNR
Microchip Technology
-
PIC10F202T-I/OT
Microchip Technology
-
ATTINY404-SSNR
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
