STMicroelectronics STM32H563IIK3Q
- Part No.:
- STM32H563IIK3Q
- Manufacturer:
- STMicroelectronics
- Category:
- Microcontrollers
- Package:
- 201-UFBGA
- Datasheet:
-
STM32H563IIK3Q.pdf
- Description:
- IC MCU 32BIT 2MB FLASH 176UFBGA
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
STM32H563IIK3Q from STMicroelectronics is a 32-bit Arm® Cortex®-M33 microcontroller with TrustZone® security, 250 MHz max clock, 2-Mbyte ECC flash, 640-Kbyte SRAM (including ECC-protected SRAM2/SRAM3), and integrated CORDIC/FMAC math accelerators. It targets secure industrial control, IoT edge nodes, and automotive body electronics requiring high-integrity firmware execution and real-time signal processing.
For engineers reviewing the STM32H563IIK3Q datasheet, STM32H563IIK3Q pinout, STM32H563IIK3Q application, or STM32H563IIK3Q equivalent, key selection criteria include TrustZone-enforced peripheral isolation, dual-bank read-while-write flash for OTA updates, 140 GPIOs with 5 V tolerance, dual DMA controllers, and hardware-accelerated cryptographic primitives (ECDSA, HASH, RNG).
Technical Context
The STM32H563IIK3Q implements Armv8-M mainline security with configurable SAU regions, enabling strict separation of secure/non-secure firmware execution. Its ART Accelerator includes 8-Kbyte instruction cache and 4-Kbyte data cache to sustain zero-wait-state operation from flash and external memories.
It integrates two independent GPDMA controllers supporting memory-to-memory, peripheral-to-memory, and memory-to-peripheral transfers with FIFO buffering. The dual 12-bit ADCs deliver up to 5 Msps sampling rate, while the CORDIC coprocessor accelerates trigonometric functions and FMAC handles FIR/IIR filtering in real time.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | Arm Cortex-M33 with TrustZone, FPU, MPU, 375 DMIPS @ 250 MHz - enables secure real-time deterministic execution and floating-point math. |
| Flash Memory | 2 Mbytes embedded flash with ECC and dual-bank RWW - supports seamless firmware updates without halting application code. |
| SRAM | 640 Kbytes total: 64-Kbyte SRAM2 (ECC), 320-Kbyte SRAM3 (flexible ECC), 4-Kbyte backup SRAM - ensures data integrity and low-power retention. |
| Math Acceleration | CORDIC + FMAC coprocessors - offloads trigonometric and filter computations from CPU, reducing latency and power. |
| Security Features | TrustZone, 8 SAU regions, SFI, ECDSA verification, NIST SP800-90B TRNG, 96-bit unique ID - meets IEC 62443-3-3 SL2 requirements. |
| Peripherals | 2×12-bit ADCs (5 Msps), 2×DACs, 2×FDCAN, 12×U(S)ART, 6×SPI, 4×I2C, 2×SAI, Octo-SPI, Ethernet MAC, USB FS/Type-C - scalable connectivity for complex edge systems. |
| Package & Pin Count | UFBGA176+25 (10 × 10 mm, 201-ball layout) - high I/O density with thermal and EMI-optimized BGA footprint. |
Pinout & Package
STM32H563IIK3Q uses a UFBGA176+25 package (10 × 10 mm, 201-ball layout) with 140 general-purpose I/Os, most 5 V-tolerant, and dedicated supply pins for VDD, VSS, VCAP, VBAT, and analog domains. Ball pitch is 0.65 mm; top-side marking includes "H563IIK3Q" and date code.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD, VDDA, VDDIO2 | Power supply inputs | 1.71–3.6 V digital/analog core and I/O domain supplies; VDDIO2 supports independent 1.08–3.6 V I/O rail for mixed-voltage interfacing. |
| VCAP1, VCAP2 | Core voltage decoupling | Connects to external 2.2 µF ceramic capacitors for SMPS/LDO output stabilization - critical for stable 250 MHz operation. |
| NRST | Active-low reset input | Asynchronous reset pin with internal pull-up; accepts external reset sources or debugger-initiated reset sequences. |
| BOOT0 | Boot mode selection | Configures boot source (system memory, flash, or SRAM); level sampled at power-on reset and after exit from Standby mode. |
| PA0–PA15, PB0–PB15, etc. | General-purpose I/Os | 140 fast GPIOs with interrupt capability; majority support 5 V tolerance and multiple alternate functions (UART, SPI, I2C, timers). |
| PC13–PC15 | RTC-related pins | PC13 = RTC_OUT, PC14/PC15 = 32.768 kHz LSE crystal connections - enable calendar functions and tamper detection in lowest power modes. |
Key Features
| Feature | Design Value |
|---|---|
| TrustZone-aware peripherals | All major peripherals (GPIO, UART, SPI, ADC, timers) are configurable as secure or non-secure - enforces hardware-isolated execution environments. |
| Secure Firmware Installation (SFI) | Hardware-verified signature check on firmware images before loading into flash - prevents unauthorized or corrupted code execution. |
| Dual-bank flash with RWW | Enables background programming of one bank while executing from the other - essential for fail-safe over-the-air (OTA) updates. |
| Flexible ECC configuration | SRAM2 (64 KB) has fixed ECC; SRAM3 (320 KB) allows per-32-byte region ECC enable/disable - balances reliability vs. memory overhead. |
| Low-power timer suite | Six LPTIMs available in Stop mode with sub-microamp current draw - supports precise timing in battery-powered applications. |
Applications
| Industrial PLC Controller | Secure IoT Gateway |
|---|---|
Use Scenario: Programmable logic controller managing motor drives, sensors, and HMI communication in factory automation. IC Role / Device Role / Timing Role: Main system controller executing real-time ladder logic, handling EtherCAT/Modbus RTU, and managing secure firmware updates. Use Value: Dual-bank flash enables zero-downtime field upgrades; TrustZone isolates safety-critical control tasks from network-facing services. |
Use Scenario: Edge gateway aggregating BLE/Zigbee sensor data, performing local AI inference, and forwarding to cloud via TLS-secured Ethernet/USB. IC Role / Device Role / Timing Role: Secure host MCU running TF-M-based PSA Certified firmware, managing crypto operations and peripheral offload. Use Value: Hardware-accelerated ECDSA and HASH reduce TLS handshake latency by >40%; CORDIC/FMAC accelerate sensor fusion algorithms. |
| Automotive Body Control Module | Medical Diagnostic Device |
Use Scenario: Central body controller managing lighting, door locks, HVAC, and CAN FD communication in passenger vehicles. IC Role / Device Role / Timing Role: Safety-compliant controller with ASIL-B capable peripherals, watchdog supervision, and secure boot chain. Use Value: FDCAN interfaces meet ISO 11898-1:2015; 96-bit UID and TRNG support vehicle identity binding and anti-cloning. |
Use Scenario: Portable ultrasound or ECG device requiring high-precision analog acquisition, real-time DSP, and HIPAA-compliant data encryption. IC Role / Device Role / Timing Role: Signal-processing hub acquiring from 12-bit ADCs, filtering with FMAC, encrypting data using PKA/HASH before storage/transmission. Use Value: 5 Msps ADC sampling captures transient waveforms; dedicated RNG and ECDSA ensure cryptographically sound patient data handling. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar high-security, high-performance MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| STM32H753IIK6 | No TrustZone; Cortex-M7 @ 480 MHz; 2-Mbyte flash, 1-Mbyte RAM; no CORDIC/FMAC; single-bank flash only. | Lacks hardware-enforced security partitioning; less suitable for PSA Level 2 or IEC 62443 deployments. | Select when raw performance > security isolation; requires software-only secure boot and peripheral access control. |
| NXP i.MX RT1176AVM8B | Cortex-M7 + Cortex-M4 dual-core; 1-GHz M7; 2-Mbyte on-chip RAM; no TrustZone on M4; different peripheral set (no Octo-SPI, no FMAC). | Higher compute throughput but fragmented security model; M4 lacks TrustZone, limiting secure peripheral access. | Prefer for asymmetric multiprocessing workloads where M7 handles AI and M4 handles real-time control - not drop-in replacement. |
Compared with STM32H563IIK3Q, the STM32H753IIK6 trades hardware security for higher clock speed and larger RAM, while the i.MX RT1176AVM8B offers dual-core flexibility at the cost of unified TrustZone enforcement across all peripherals.
Availability
STM32H563IIK3Q is available at Aetrix Electronics and suitable for industrial PLCs, secure IoT gateways, automotive body control modules, and medical diagnostic devices requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.
Supply support for STM32H563IIK3Q includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power management ICs, sensors, and analog components for industrial, automotive, and consumer markets.
The STM32H5 series is ST's flagship secure MCU line built on Arm Cortex-M33 with TrustZone, targeting applications demanding PSA Certified Level 2 compliance, functional safety readiness (IEC 61508), and hardware-rooted security for edge intelligence.
FAQ
What is the maximum operating frequency and associated performance metric?
The STM32H563IIK3Q operates at up to 250 MHz with an Arm Cortex-M33 core delivering 375 DMIPS (Dhrystone 2.1) and 1023 CoreMark®. This performance is sustained via the 8-Kbyte instruction cache and ART Accelerator, enabling zero-wait-state execution from embedded flash memory.
Does STM32H563IIK3Q support over-the-air (OTA) firmware updates without service interruption?
Yes. Its dual-bank flash architecture with read-while-write capability allows one bank to execute active firmware while the other is being reprogrammed. Combined with Secure Firmware Installation (SFI) and TrustZone-protected update handlers, it enables authenticated, atomic, and fail-safe OTA updates.
How does the TrustZone implementation differ from earlier STM32 families like the H7 series?
Unlike the H7 (which lacks TrustZone), the H563IIK3Q implements Armv8-M mainline TrustZone with eight configurable SAU regions, GTZC-controlled peripheral security attribution, and TrustZone-aware debug authentication. All major peripherals - including GPIO, ADC, timers, and communication interfaces - can be assigned secure/non-secure attributes at runtime.
What external memory interfaces are supported, and what is the maximum bandwidth achievable?
The device supports Flexible Memory Controller (FMC) for SRAM, PSRAM, SDRAM/LPSDR, FRAM, and NOR/NAND, plus Octo-SPI for serial PSRAM/NOR/flash. With Octo-SPI in octal DDR mode, peak bandwidth reaches 800 MB/s; FMC with SDRAM achieves up to 200 MB/s depending on configuration and clock tuning.
STM32H563IIK3Q Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Package/Case:
- 201-UFBGA
- Series:
- STM32H5
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- ARM® Cortex®-M33
- Core Size:
- 32-Bit
- Speed:
- 250MHz
- Connectivity:
- CANbus, Ethernet, FIFO, I2C, IrDA, LINbus, SCI, SDIO, SMBus, SPI, UART/USART, USB
- Peripherals:
- Brown-out Detect/Reset, DMA, I2S, PDR, POR, PWM, SHA, TRNG, Voltage Detect, WDT
- Number of I/O:
- 139
- Program Memory Size:
- 2MB (2M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 640K x 8
- Voltage - Supply (Vcc/Vdd):
- 1.71V ~ 3.6V
- Data Converters:
- A/D 20x12b SAR; D/A 2x12b
- Oscillator Type:
- External, Internal
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
STM32H563IIK3Q FAQ
1.How can I place an order for STM32H563IIK3Q through Aetrix?
Please submit a Request for Quotation (RFQ) for STM32H563IIK3Q on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for STM32H563IIK3Q reliable?
The price and inventory of STM32H563IIK3Q are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for STM32H563IIK3Q is usually 5 days.
3.What payment methods are accepted for STM32H563IIK3Q?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for STM32H563IIK3Q transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for STM32H563IIK3Q?
STM32H563IIK3Q orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your STM32H563IIK3Q order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for STM32H563IIK3Q?
For technical support, including STM32H563IIK3Q datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your STM32H563IIK3Q requirements.
6.How does Aetrix verify that STM32H563IIK3Q is sourced from the original manufacturer or authorized distributors?
All STM32H563IIK3Q products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that STM32H563IIK3Q meets industry standards.
7.What is the process for return or replacement of STM32H563IIK3Q?
All STM32H563IIK3Q units undergo pre-shipment inspection (PSI). If there is an issue with STM32H563IIK3Q, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The STM32H563IIK3Q part is unused and in its original packaging.
Return procedure for STM32H563IIK3Q:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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