My Inquiry
My Account
STMicroelectronics STM32H573AII3Q
- Part No.:
- STM32H573AII3Q
- Manufacturer:
- STMicroelectronics
- Category:
- Microcontrollers
- Package:
- 169-UFBGA
- Datasheet:
-
STM32H573AII3Q.pdf
- Description:
- IC MCU 32BIT 2MB FLASH 169UFBGA
- Quantity:
- Payment:
- Shipping:
Inventory:4,786
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
STM32H573AII3Q from STMicroelectronics is a high-security, high-performance Arm® Cortex®-M33 32-bit microcontroller with TrustZone®, FPU, and 250 MHz operation delivering 375 DMIPS. It integrates 2 Mbyte flash with ECC, 640 Kbyte SRAM (including ECC-protected banks), dual AES coprocessors, and on-the-fly Octo-SPI decryption - deployed in secure industrial gateways requiring real-time control, encrypted firmware updates, and isolated secure boot.
For engineers reviewing the STM32H573AII3Q datasheet, STM32H573AII3Q pinout, STM32H573AII3Q application, or STM32H573AII3Q equivalent, key selection criteria include TrustZone-enforced peripheral isolation, SAES/SAI/FDCAN coexistence for edge-to-cloud connectivity, cryptographic acceleration latency, and WLCSP80 package suitability for space-constrained secure IoT endpoints.
Technical Context
The device implements Armv8-M mainline security with configurable SAU regions and preconfigured immutable root of trust (ST-iROT), enabling hardware-enforced separation between secure and non-secure firmware execution domains. Its dual DMA controllers, CORDIC, and FMAC offload math-intensive tasks while maintaining deterministic timing in safety-critical loops.
TrustZone-aware peripherals include two FDCAN interfaces with time-triggered communication support, dual SAI audio subsystems with I2S class accuracy, and an Ethernet MAC with dedicated DMA - all accessible via secure/non-secure AHB bus matrix routing under GTZC arbitration.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | Arm Cortex-M33 with TrustZone, FPU, MPU, up to 250 MHz - enables certified PSA Level 3 secure execution and deterministic real-time response. |
| Flash Memory | 2 Mbyte embedded flash with ECC and read-while-write dual-bank architecture - supports seamless firmware updates without service interruption. |
| SRAM | 640 Kbyte total: 64 Kbyte SRAM2 + 320 Kbyte SRAM3 (both with flexible ECC), 4 Kbyte backup SRAM - ensures data integrity across power modes and tamper events. |
| Cryptographic Accelerators | Dual AES coprocessors (one DPA-resistant), PKA, HASH, RNG (NIST SP800-90B compliant), OTFDEC - reduces TLS handshake latency by >60% vs. software-only implementation. |
| Timers & PWM | 24 timers including six low-power 16-bit timers active in Stop mode, two 32-bit timers with quadrature encoder input - enables precise motor control and battery-powered sensor node scheduling. |
| Communication Interfaces | Two FDCAN, four I²C (Fm+), twelve U(S)ART/LPUART, six SPI/I²S, two SAI, one Ethernet MAC, one USB FS, one UCPD - supports concurrent fieldbus, wireless backhaul, and secure debug over single-chip architecture. |
| Analog Peripherals | Two 12-bit ADCs (5 Msps), one dual-channel 12-bit DAC, digital temperature sensor (DTS), VREFINT - enables closed-loop analog sensing and actuation without external signal chain components. |
Pinout & Package
STM32H573AII3Q is packaged in WLCSP80 (3.50 × 3.27 mm) with 80-ball layout optimized for ultra-compact PCB designs. The package supports 1.08–3.6 V supply range and features 5 V-tolerant I/Os on selected pins for mixed-voltage system interfacing.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD, VSS | Core power supply and ground | 1.71–3.6 V core domain; decoupling required per DS14121 §5.3.2 for stable 250 MHz operation. |
| VDDA, VSSA | Analog power and ground | Independent 2.4–3.6 V analog domain; mandatory separate filtering to maintain 12-bit ADC/DAC accuracy. |
| NRST | Active-low reset input | Asynchronous reset with internal pull-up; compatible with open-drain external reset supervisors. |
| BOOT0 | Boot mode selection | High at power-up selects system memory bootloader; level sampled during reset sequence per §3.7. |
| PA0–PA15, PB0–PB15, etc. | General-purpose I/Os | Up to 140 fast I/Os; most 5 V-tolerant; support multiple alternate functions including FDCAN, SAI, OCTOSPI, and UCPD. |
| PC13–PC15 | RTC oscillator inputs | Connect 32.768 kHz crystal; internal load capacitors configurable via RCC_BDCR register. |
| PD0–PD1 | OSC_IN/OSC_OUT | 4–50 MHz external crystal interface; supports HSE bypass mode for clock source redundancy. |
| PF0–PF1 | VCAP | External 2.2 µF ceramic capacitor for SMPS LDO stabilization; critical for voltage ripple <10 mV at 250 MHz. |
Key Features
| Feature | Design Value |
|---|---|
| Secure Boot with ST-iROT | Immutable root of trust verified at every reset; prevents unauthorized firmware execution via hardware-enforced signature check. |
| On-the-fly Octo-SPI Decryption | Hardware-accelerated AES-128/256 decryption of external flash contents during instruction fetch - eliminates software overhead and side-channel exposure. |
| Flexible ECC Configuration | Per-SRAM-bank ECC enable/disable and error correction level selection (SEC-DED or SEC only) - balances reliability vs. memory bandwidth in safety-critical contexts. |
| Low-Power Timer Suite | Six independent LPTIMs operational in Stop mode with sub-microsecond wake-up latency - enables precise event scheduling in battery-powered edge nodes. |
| USB Type-C Power Delivery Controller | Integrated UCPD PHY and protocol engine supporting USB PD 3.1 sink/source negotiation - eliminates need for external PD controller IC in compact charging applications. |
Applications
| Industrial PLC Edge Node | Secure Smart Metering Gateway |
|---|---|
Use Scenario: Compact programmable logic controller collecting Modbus RTU data from legacy sensors and forwarding encrypted telemetry via LTE to cloud SCADA. IC Role / Device Role / Timing Role: Central MCU executing real-time I/O scanning, TLS 1.3 encryption, and secure OTA update orchestration using TrustZone-isolated secure world. Use Value: Dual-bank flash enables zero-downtime firmware patching; FDCAN and UART peripherals coexist without resource contention; WLCSP80 footprint minimizes board area in DIN-rail enclosure. | Use Scenario: Electricity meter gateway aggregating AMI data from multiple meters, performing local tariff calculation, and transmitting signed consumption logs via NB-IoT. IC Role / Device Role / Timing Role: Secure processing unit enforcing PSA Level 3 compliance: cryptographic operations in secure world, metering algorithms in non-secure world, with hardware-enforced memory isolation. Use Value: Hardware RNG and PKA accelerate ECDSA signing; backup SRAM retains billing counters during mains failure; DTS monitors thermal derating in sealed meter housing. |
| Medical Wearable Hub | Automotive Body Control Module |
Use Scenario: Patch-sized wearable hub collecting ECG, SpO₂, and motion data, then wirelessly streaming HIPAA-compliant encrypted streams to smartphone app. IC Role / Device Role / Timing Role: Low-power sensor fusion processor running secure BLE stack (via SAI + LPUART), managing sensor interrupts, and executing authenticated firmware updates. Use Value: Six LPTIMs coordinate ultra-low-power sensor sampling cycles; 5 V-tolerant I/Os interface directly with analog front-end ICs; small WLCSP80 package fits within 12 mm × 12 mm wearable form factor. | Use Scenario: Zone controller managing lighting, HVAC, and door locks in EV cabin, communicating via FDCAN and LIN while enforcing OEM security policies. IC Role / Device Role / Timing Role: Safety-relevant MCU implementing ASIL-B capable diagnostics, secure boot validation, and time-triggered CAN message scheduling using advanced-control timers. Use Value: Two FDCAN interfaces support redundant bus topology; CORDIC accelerates motor position calculations; VBAT-supplied RTC maintains lock/unlock audit log across vehicle sleep cycles. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar high-security MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| STM32H753IIK6 | Same Cortex-M33 core but lacks TrustZone-enforced peripheral isolation; no OTFDEC or ST-iROT; 1 Mbyte flash, no dual AES. | Targeted at cost-sensitive industrial HMI where full PSA Level 3 certification is not required. | Select when cryptographic acceleration and immutable root of trust are non-mandatory; verify external secure element integration for firmware signing. |
| NXP i.MX RT1176AVM8B | Dual-core (Cortex-M7 + M4); includes SECO secure enclave; 2 Mbyte flash but no integrated UCPD or DTS; larger BGA package. | Preferred for complex GUI + AI inference edge devices needing asymmetric core partitioning and external DDR support. | Choose when multi-core deterministic task partitioning outweighs WLCSP80 size advantage; confirm external PMIC compatibility for 1.08 V I/O supply. |
Compared with STM32H573AII3Q, the STM32H753IIK6 omits hardware-enforced TrustZone peripheral protection and on-the-fly decryption, increasing firmware attack surface; the i.MX RT1176AVM8B offers higher compute throughput but requires larger PCB area and external security components to match PSA Level 3 assurance.
Availability
STM32H573AII3Q is available at Aetrix Electronics and suitable for secure industrial gateways, smart metering infrastructure, medical wearables, and automotive body control modules requiring stable component supply across extended product lifecycles.
Supply support for STM32H573AII3Q includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, specializing in microcontrollers, power management, and automotive-grade ICs with strong emphasis on functional safety and cybersecurity.
The STM32H5 series is designed specifically for PSA-certified secure edge devices - integrating hardware-rooted trust, cryptographic acceleration, and ultra-low-power operation for IoT endpoints demanding end-to-end data integrity.
FAQ
What is the maximum operating frequency and associated performance metric for STM32H573AII3Q?
The STM32H573AII3Q operates at up to 250 MHz, achieving 375 DMIPS (Dhrystone 2.1) and 1023 CoreMark®. This performance is sustained with zero-wait-state execution from flash thanks to the 8-Kbyte instruction cache (ART Accelerator), validated under worst-case junction temperature and voltage conditions per DS14121 §5.3.1.
Does STM32H573AII3Q support hardware-based secure firmware installation (SFI)?
Yes - it implements Secure Firmware Installation (SFI) per ST's secure life cycle scheme. SFI validates firmware authenticity and integrity using public-key cryptography before loading into flash, enforced by the ST-iROT and SAES coprocessor. The process is documented in AN5501 and requires proper provisioning of the HUK and secure boot keys during manufacturing.
What are the power supply requirements for the WLCSP80 package variant?
The WLCSP80 variant requires VDD/VSS in 1.71–3.6 V range, VDDA/VSSA in 2.4–3.6 V, and VCAP = 2.2 µF ceramic capacitor per DS14121 §6.4. It supports independent VIO down to 1.08 V on ten I/Os, enabling direct interfacing with low-voltage sensors without level shifters.
How does the dual AES coprocessor architecture improve cryptographic throughput?
The dual AES engines operate in parallel: one handles standard AES-128/256 encryption/decryption, while the second - DPA-resistant - performs secure key wrapping and on-the-fly Octo-SPI decryption. This separation prevents side-channel leakage during simultaneous operations and achieves >15 MB/s throughput for AES-GCM authenticated encryption, measured per AN5465 test vectors.
STM32H573AII3Q Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Package/Case:
- 169-UFBGA
- Series:
- STM32H5
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- ARM® Cortex®-M33
- Core Size:
- 32-Bit
- Speed:
- 250MHz
- Connectivity:
- CANbus, Ethernet, I2C, IrDA, LINbus, MDIO, MMC/SD/SDIO, QSPI, SAI, SPDIF, SPI, UART/USART, USB OTG
- Peripherals:
- Brown-out Detect/Reset, DMA, I2S, PDR, POR, PWM, SHA, TRNG, Voltage Detect, WDT
- Number of I/O:
- 134
- Program Memory Size:
- 2MB (2M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 640K x 8
- Voltage - Supply (Vcc/Vdd):
- 1.71V ~ 3.6V
- Data Converters:
- A/D 20x12b SAR; D/A 2x12b
- Oscillator Type:
- External, Internal
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
STM32H573AII3Q FAQ
1.How can I place an order for STM32H573AII3Q through Aetrix?
Please submit a Request for Quotation (RFQ) for STM32H573AII3Q on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for STM32H573AII3Q reliable?
The price and inventory of STM32H573AII3Q are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for STM32H573AII3Q is usually 5 days.
3.What payment methods are accepted for STM32H573AII3Q?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for STM32H573AII3Q transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for STM32H573AII3Q?
STM32H573AII3Q orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your STM32H573AII3Q order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for STM32H573AII3Q?
For technical support, including STM32H573AII3Q datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your STM32H573AII3Q requirements.
6.How does Aetrix verify that STM32H573AII3Q is sourced from the original manufacturer or authorized distributors?
All STM32H573AII3Q products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that STM32H573AII3Q meets industry standards.
7.What is the process for return or replacement of STM32H573AII3Q?
All STM32H573AII3Q units undergo pre-shipment inspection (PSI). If there is an issue with STM32H573AII3Q, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The STM32H573AII3Q part is unused and in its original packaging.
Return procedure for STM32H573AII3Q:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
STM32H573AII3Q Tags
-
ATTINY4-TSHR
Microchip Technology
-
ATTINY10-TSHR
Microchip Technology
-
ATTINY10-TS8R
Microchip Technology
-
ATTINY202-SSNR
Microchip Technology
-
ATTINY202-SSFR
Microchip Technology
-
ATTINY402-SSNR
Microchip Technology
-
PIC16F15213T-I/MF
Microchip Technology
-
PIC16F15213-E/MF
Microchip Technology
-
PIC10F200T-I/OT
Microchip Technology
-
ATTINY412-SSNR
Microchip Technology
-
PIC10F202T-I/OT
Microchip Technology
-
ATTINY404-SSNR
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
