STMicroelectronics STM32H573AII6
- Part No.:
- STM32H573AII6
- Manufacturer:
- STMicroelectronics
- Category:
- Microcontrollers
- Package:
- 169-UFBGA
- Datasheet:
-
STM32H573AII6.pdf
- Description:
- IC MCU 32BIT 2MB FLASH 169UFBGA
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
STM32H573AII6 from STMicroelectronics is a high-security, high-performance Arm® Cortex®-M33 32-bit microcontroller with TrustZone®, FPU, and 250 MHz max clock speed. It integrates 2 Mbyte flash with ECC, 640 Kbyte SRAM (including ECC-protected SRAM2/SRAM3), dual AES coprocessors, PSA Level 3/SESIP3 certification, and on-the-fly Octo-SPI decryption - deployed in secure industrial gateways requiring real-time control, encrypted firmware updates, and isolated secure boot.
For engineers reviewing the STM32H573AII6 datasheet, STM32H573AII6 pinout, STM32H573AII6 application, or STM32H573AII6 equivalent, key selection criteria include TrustZone-enforced peripheral isolation, 250 MHz deterministic execution with ART cache, dual DMA controllers for offloading, hardware-accelerated CORDIC/FMAC for motor control math, and support for secure over-the-air (OTA) firmware upgrades via TF-M.
Technical Context
The STM32H573AII6 implements Armv8-M mainline security with configurable SAU regions and preconfigured immutable root of trust (ST-iROT), enabling hardware-enforced separation between secure and non-secure firmware domains. Its dual-core-aware debug architecture supports authenticated SWD/JTAG access with flexible life cycle management.
It features two independent DMA controllers with FIFOs, an ART Accelerator with 8-Kbyte instruction cache and 4-Kbyte data cache, and dual cryptographic accelerators: one DPA-resistant AES engine and a public key accelerator (PKA) supporting RSA/ECC operations - all accessible only under TrustZone-secured privilege levels.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | Arm Cortex-M33 with TrustZone, FPU, MPU, up to 250 MHz - enables deterministic real-time task scheduling and secure peripheral access control. |
| Flash Memory | 2 Mbyte embedded flash with ECC and read-while-write capability - supports concurrent firmware update and execution without interruption. |
| SRAM | 640 Kbyte total: 64 Kbyte SRAM2 (ECC), 320 Kbyte SRAM3 (flexible ECC), 4 Kbyte backup SRAM - provides fault-tolerant data retention in low-power modes. |
| Cryptographic Acceleration | Dual AES engines (one DPA-resistant), PKA, HASH, RNG (NIST SP800-90B compliant), OTFDEC - enables secure boot, encrypted OTA, and TLS offload. |
| Timers & PWM | 24 timers including six low-power 16-bit timers active in Stop mode, two 32-bit timers with quadrature encoder input - suitable for motor control and precision timing in battery-powered edge nodes. |
| Analog Peripherals | Two 12-bit ADCs (5 Msps), one dual-channel 12-bit DAC, digital temperature sensor (DTS), VREFINT - supports closed-loop analog sensing and actuation without external ICs. |
| Communication Interfaces | Four I²C (Fm+), one I³C, twelve USART/LPUART, six SPI/I²S, two SAI, two FDCAN, Ethernet MAC, USB FS host/device, UCPD - enables multi-protocol connectivity in industrial HMI and gateway applications. |
Pinout & Package
The STM32H573AII6 is packaged in a 80-ball WLCSP (3.50 × 3.27 mm, pitch 0.4 mm), optimized for space-constrained secure edge devices. Ballout supports full peripheral mapping including dual FDCAN, Octo-SPI, Ethernet PHY interface, and TrustZone-secured debug pins.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD, VSS | Core power supply / ground | 1.71–3.6 V operation; decoupling required per datasheet Section 5.3.6 for stable 250 MHz execution. |
| VDDA, VSSA | Analog domain supply / ground | Independent analog rail for ADC/DAC operation; must be filtered to meet 12-bit accuracy requirements. |
| NRST | Active-low reset input | Asynchronous reset with internal pull-up; compatible with external reset supervisors and brown-out detection circuits. |
| BOOT0 | Boot mode selection | High at power-up selects system memory boot; used with ST-LINK for DFU or secure bootloader entry. |
| PA13/PA14 | SWDIO/SWCLK debug interface | Authenticated serial wire debug pins - require secure debug authentication before access in production life cycle. |
| PC10/PC11 | FDCAN1_RX/FDCAN1_TX | Dedicated CAN FD transceiver interface with bit-rate up to 5 Mbps - supports functional safety diagnostics in automotive-grade gateways. |
| PD0/PD1 | OSC_IN/OSC_OUT | External 4–50 MHz crystal connection for high-precision clock source - required for USB, Ethernet, and audio timing accuracy. |
Key Features
| Feature | Design Value |
|---|---|
| TrustZone-enforced peripheral isolation | Eight configurable SAU regions enable hardware partitioning of peripherals (e.g., FDCAN, Octo-SPI) between secure and non-secure firmware domains. |
| On-the-fly Octo-SPI decryption (OTFDEC) | Decrypts external flash contents in real time using AES-128/256 keys stored in secure memory - eliminates need for RAM-based decryption buffers. |
| Secure firmware installation (SFI) | Hardware-verified signature check during boot ensures only cryptographically signed images execute - prevents unauthorized firmware injection. |
| CORDIC + FMAC acceleration | Hardware trigonometric and filter computation reduces CPU load by >70% in motor control loops - enables 20 kHz PWM update rates with <1 µs latency. |
| Flexible power management | SMPS regulator support with scalable output voltage (0.8–1.2 V) and multiple low-power modes (Stop, Standby with RTC/VBAT) - extends battery life in portable secure IoT nodes. |
Applications
| Industrial Gateway | Secure Edge Node |
|---|---|
Use Scenario: Field-deployed protocol translator aggregating Modbus RTU, CAN FD, and Ethernet/IP traffic into cloud-connected MQTT streams. IC Role / Device Role / Timing Role: Main application processor executing Linux RTOS, managing secure TLS tunnels, and enforcing policy-based data routing via TrustZone-isolated drivers. Use Value: Dual AES engines accelerate TLS 1.3 handshake and payload encryption; OTFDEC enables secure firmware updates from encrypted external flash without exposing keys in RAM. |
Use Scenario: Battery-powered smart sensor node monitoring vibration, temperature, and humidity in hazardous environments with remote firmware updates. IC Role / Device Role / Timing Role: Low-power MCU running TF-M secure bootloader and sensor fusion firmware, waking periodically via LPTIM to sample ADC/DTS and transmit via LPUART. Use Value: 4 Kbyte backup SRAM retains calibration data across deep sleep; PSA Level 3 certification satisfies IEC 62443-3-3 requirements for secure device identity and attestation. |
| Medical Data Logger | Automotive Diagnostic Tool |
Use Scenario: Portable ECG/SpO₂ data logger storing raw biosignals locally and transmitting anonymized summaries via BLE gateway. IC Role / Device Role / Timing Role: Secure acquisition controller with isolated ADC sampling path, encrypted storage in flash, and hardware-secured key generation for patient data signing. Use Value: NIST SP800-90B-compliant RNG generates cryptographically strong keys; dual 12-bit ADCs achieve 5 Msps aggregate throughput for multi-lead signal capture. |
Use Scenario: Handheld OBD-II scanner supporting UDS diagnostics over FDCAN and firmware updates via USB Type-C with Power Delivery negotiation. IC Role / Device Role / Timing Role: Dual-interface controller managing FDCAN physical layer timing, USB PD policy engine, and secure flash reprogramming via UCPD. Use Value: UCPD peripheral handles USB PD 3.1 communication natively; FDCAN controllers meet ISO 11898-1:2015 timing jitter specs (<±1 ns) for reliable diagnostic message transmission. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar high-security MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| STM32H753VI | Lacks TrustZone, PSA Level 3, OTFDEC, and dual AES; uses Cortex-M7 (no Armv8-M security extensions); 1 Mbyte flash, no SFI or ST-iROT. | Suitable for non-certified industrial control where security is software-managed; cannot replace STM32H573AII6 in PSA-compliant deployments. | Select only if TrustZone isolation, secure boot certification, and hardware crypto acceleration are not required. |
| NXP i.MX RT1189 | Arm Cortex-M85 core, dual-band Wi-Fi/BLE co-processor, no OTFDEC; uses SECO secure enclave instead of TrustZone; different pinout and memory map. | Better for wireless edge AI inference; lacks native FDCAN/Ethernet MAC integration and requires external PHY for wired industrial protocols. | Choose when integrated wireless connectivity outweighs deterministic real-time control and industrial protocol stack depth. |
Compared with STM32H573AII6, the STM32H753VI omits hardware-enforced security primitives essential for certified secure boot, while the i.MX RT1189 trades industrial interface density and deterministic timing for wireless flexibility - making STM32H573AII6 uniquely suited for wired, safety-critical, field-upgradable edge gateways.
Availability
STM32H573AII6 is available at Aetrix Electronics and suitable for secure industrial gateways, medical data loggers, automotive diagnostic tools, and battery-powered edge nodes requiring stable component supply throughout product lifecycles.
Supply support for STM32H573AII6 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, specializing in microcontrollers, power management, sensors, and automotive ICs with over 40 years of industrial design-in experience.
The STM32H5 series is ST's flagship high-security MCU line targeting PSA Level 3 and SESIP3-certified applications - designed specifically for zero-trust architectures in industrial automation, healthcare, and automotive telematics.
FAQ
What is the maximum operating frequency and how is it achieved?
The STM32H573AII6 achieves 250 MHz maximum CPU frequency using its internal 64 MHz HSI oscillator multiplied by the PLL, or an external 4–50 MHz crystal. The ART Accelerator's 8-Kbyte instruction cache enables true 0-wait-state execution from flash, sustaining 375 DMIPS (1.5 DMIPS/MHz) without performance throttling due to memory latency.
Does this part support secure firmware updates over the air (OTA)?
Yes - the STM32H573AII6 supports secure OTA updates via its TrustZone-secured TF-M implementation, SFI verification, and OTFDEC engine. Encrypted firmware images stored in external Octo-SPI flash are decrypted on-the-fly during execution, with signature validation performed in secure ROM before loading into protected SRAM.
What debug interfaces are available and are they secure?
It supports Serial Wire Debug (SWD) and JTAG via PA13/PA14, with authenticated debug enabled by default. Secure debug authentication requires valid credentials programmed into the device's secure life cycle registers - unauthenticated access is blocked in production mode, preventing unauthorized firmware extraction or modification.
How does the dual AES coprocessor improve system-level security?
The dual AES engines allow parallel encryption/decryption operations: one DPA-resistant unit handles sensitive key material (e.g., TLS session keys), while the second manages bulk data (e.g., OTA payloads). This separation prevents side-channel leakage across security domains and enables simultaneous secure boot verification and runtime crypto operations without CPU intervention.
STM32H573AII6 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Package/Case:
- 169-UFBGA
- Series:
- STM32H5
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- ARM® Cortex®-M33
- Core Size:
- 32-Bit
- Speed:
- 250MHz
- Connectivity:
- CANbus, Ethernet, I2C, IrDA, LINbus, MDIO, MMC/SD/SDIO, QSPI, SAI, SPDIF, SPI, UART/USART, USB OTG
- Peripherals:
- Brown-out Detect/Reset, DMA, I2S, PDR, POR, PWM, SHA, TRNG, Voltage Detect, WDT
- Number of I/O:
- 136
- Program Memory Size:
- 2MB (2M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 640K x 8
- Voltage - Supply (Vcc/Vdd):
- 1.71V ~ 3.6V
- Data Converters:
- A/D 20x12b SAR; D/A 2x12b
- Oscillator Type:
- External, Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
STM32H573AII6 FAQ
1.How can I place an order for STM32H573AII6 through Aetrix?
Please submit a Request for Quotation (RFQ) for STM32H573AII6 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for STM32H573AII6 reliable?
The price and inventory of STM32H573AII6 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for STM32H573AII6 is usually 5 days.
3.What payment methods are accepted for STM32H573AII6?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for STM32H573AII6 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for STM32H573AII6?
STM32H573AII6 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your STM32H573AII6 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for STM32H573AII6?
For technical support, including STM32H573AII6 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your STM32H573AII6 requirements.
6.How does Aetrix verify that STM32H573AII6 is sourced from the original manufacturer or authorized distributors?
All STM32H573AII6 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that STM32H573AII6 meets industry standards.
7.What is the process for return or replacement of STM32H573AII6?
All STM32H573AII6 units undergo pre-shipment inspection (PSI). If there is an issue with STM32H573AII6, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The STM32H573AII6 part is unused and in its original packaging.
Return procedure for STM32H573AII6:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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