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STMicroelectronics STM32H573IIT3Q
- Part No.:
- STM32H573IIT3Q
- Manufacturer:
- STMicroelectronics
- Category:
- Microcontrollers
- Package:
- 176-LQFP
- Datasheet:
-
STM32H573IIT3Q.pdf
- Description:
- IC MCU 32BIT 2MB FLASH 176LQFP
- Quantity:
- Payment:
- Shipping:
Inventory:1,155
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Product details
Overview
STM32H573IIT3Q from STMicroelectronics is a high-security, high-performance Arm® Cortex®-M33 32-bit microcontroller with TrustZone®, FPU, and cryptographic accelerators. It operates at up to 250 MHz (375 DMIPS), integrates 2 Mbyte flash with ECC and 640 Kbyte SRAM (including ECC-protected SRAM2/SRAM3), and supports on-the-fly Octo-SPI decryption - deployed in secure industrial gateways requiring real-time control, encrypted firmware updates, and hardware-rooted trust.
For engineers reviewing the STM32H573IIT3Q datasheet, STM32H573IIT3Q pinout, STM32H573IIT3Q application, or STM32H573IIT3Q equivalent, key selection criteria include TrustZone-enforced peripheral isolation, dual AES coprocessors (one DPA-resistant), PSA Level 3/SESIP3 certification, and support for secure boot via ST-iROT and HUK-based secure data storage.
Technical Context
The STM32H573IIT3Q implements a dual-bank flash architecture enabling true read-while-write operation, with one bank supporting 100K write cycles for data logging. Its ART Accelerator includes separate 8-Kbyte instruction cache and 4-Kbyte data cache, eliminating wait states for flash execution and accelerating external memory access.
Security is architected around Armv8-M TrustZone with eight configurable SAU regions, GTZC-managed peripheral protection, and immutable root of trust (ST-iROT). Cryptographic offload includes DPA-resistant PKA, dual AES engines, HASH accelerator, and OTFDEC for serial memory decryption - all accessible only from secure world without software bypass.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | Arm Cortex-M33 with TrustZone, FPU, MPU, 250 MHz max frequency (375 DMIPS @ Dhrystone 2.1) |
| Memory | 2 Mbyte flash with ECC + two-bank RWW; 640 Kbyte SRAM (64 Kbyte SRAM2 + 320 Kbyte SRAM3, both with flexible ECC) |
| Crypto Acceleration | Dual AES engines (one DPA-resistant), PKA, HASH, RNG (NIST SP800-90B compliant), OTFDEC for Octo-SPI |
| Security Certification | PSA Certified Level 3 and SESIP3 assurance target; secure debug authentication; ST-iROT immutable boot |
| Peripherals | 2× FDCAN, 12× U(S)ART, 4× I²C Fm+, 2× SAI, 2× ADC (12-bit, 5 Msps), 2× DAC, Ethernet MAC, USB FS host/device, UCPD |
| Power & Packaging | 1.71–3.6 V supply; LQFP176 package (24 × 24 mm); -40°C to +105°C industrial temperature grade |
Pinout & Package
LQFP176 (24 × 24 mm, 0.5 mm pitch) package with exposed thermal pad. Pin count: 176 leads. Compatible with standard reflow profiles per ECOPACK2.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD, VDDA, VDDIO2 | Power supply inputs | Separate domains for digital core (VDD), analog (VDDA), and I/O (VDDIO2); enable mixed-signal noise isolation and flexible voltage scaling |
| VSS, VSSA, VSSIO2 | Ground returns | Dedicated ground planes per domain reduce coupling; critical for ADC/DAC accuracy and EMI compliance |
| NRESET | Active-low reset input | Asynchronous reset with internal pull-up; supports external reset supervisor and brown-out detection coordination |
| BOOT0 | Boot mode selection | Configures primary boot source (system memory, flash, or embedded SRAM); sampled at power-on reset |
| PA13/PA14 | SWD debug interface | Serial Wire Debug (SWD) pins with dedicated trace capability; support authenticated debug access under TrustZone policy |
| PC14/PC15 | Low-speed external oscillator | Connects 32.768 kHz crystal for RTC and low-power clock tree; supports calibration and tamper detection |
Key Features
| Feature | Design Value |
|---|---|
| TrustZone-enforced peripheral isolation | Eight SAU-configurable memory/peripheral regions ensure secure world access control - prevents unauthorized DMA or register access to crypto engines or OTP |
| On-the-fly Octo-SPI decryption (OTFDEC) | Hardware-accelerated AES-128/256 decryption of external serial flash/NOR/PSRAM without CPU involvement - enables secure code execution from external memory |
| Secure firmware installation (SFI) | Immutable boot flow validates firmware signature using ST-iROT and HUK-derived keys before loading - blocks unsigned or tampered images |
| Dual AES coprocessors | One general-purpose AES engine + one DPA-resistant engine for side-channel-secure key wrapping and TLS handshake acceleration |
| Flexible ECC SRAM configuration | SRAM3 supports programmable ECC granularity (full block or per-word), balancing error correction strength against latency overhead for safety-critical buffers |
Applications
| Industrial Gateway Security | Secure Edge AI Node |
|---|---|
Use Scenario: Field-deployed gateway aggregating Modbus, CAN, and Ethernet traffic while enforcing zero-trust device onboarding. IC Role / Device Role / Timing Role: Root-of-trust anchor managing secure boot, encrypted OTA updates, and hardware-isolated TLS stack execution. Use Value: PSA Level 3-certified crypto acceleration reduces TLS handshake latency by >40% vs. software-only stacks; OTFDEC enables trusted execution from cost-effective external flash. |
Use Scenario: Battery-powered edge node performing local inference on sensor fusion data with over-the-air model updates. IC Role / Device Role / Timing Role: Secure runtime environment hosting TF-M-based trusted applications, isolating ML inference engine from untrusted OS services. Use Value: Dual AES + PKA offloads asymmetric key exchange and symmetric payload encryption, extending battery life by minimizing CPU wake time during secure comms. |
| Medical Data Logger | Smart Energy Meter |
Use Scenario: HIPAA-compliant wearable logger capturing ECG, temperature, and motion data with encrypted local storage. IC Role / Device Role / Timing Role: Trusted data acquisition controller with secure ADC sampling, encrypted SRAM buffering, and tamper-evident backup registers. Use Value: Hardware unique key (HUK) binds encryption keys to silicon identity; 32-bit tamper-detect registers log physical intrusion attempts for audit compliance. |
Use Scenario: Revenue-grade meter with DLMS/COSEM protocol stack, remote firmware update, and anti-tampering features. IC Role / Device Role / Timing Role: Secure metering SoC managing metrology ADC, secure timekeeping (RTC + LSE), and encrypted communication with utility backend. Use Value: ST-iROT and secure debug authentication prevent cloning or firmware rollback; VBAT-backed 32 backup registers retain billing counters during main power loss. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar high-security MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| STM32H753IIK6 | Same LQFP176 package; Cortex-M7 core (480 MHz), no TrustZone, single AES engine, no OTFDEC or PSA Level 3 cert | Lacks hardware-enforced secure world isolation; requires software-based security partitioning | Select when raw performance > certified security; not suitable for PSA/SESIP-regulated deployments |
| NXP i.MX RT1176DVMAA | Arm Cortex-M7 + M4 dual-core; no TrustZone on M7, but CSEc security subsystem; different package (BGA289), no OTFDEC | Relies on CSEc for crypto; lacks immutable root of trust and ST-iROT boot enforcement | Prefer for heterogeneous compute workloads; avoid where PSA Level 3 certification is mandatory |
Compared with STM32H573IIT3Q, the STM32H753IIK6 trades certified security for higher clock speed and larger SRAM, while the i.MX RT1176DVMAA offers dual-core flexibility but requires additional validation effort to meet PSA Level 3 requirements - making the H573 the only drop-in solution for pre-certified secure boot and encrypted external memory execution.
Availability
STM32H573IIT3Q is available at Aetrix Electronics and suitable for industrial gateways, medical data loggers, smart energy meters, and secure edge AI nodes requiring stable component supply across extended product lifecycles.
Supply support for STM32H573IIT3Q includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power management ICs, sensors, and automotive semiconductors.
The STM32H5 series targets high-assurance embedded systems demanding PSA Level 3/SESIP3 certification, combining Arm TrustZone with ST's proprietary secure boot (ST-iROT), hardware crypto accelerators, and tamper-aware peripherals for regulated industrial and medical applications.
FAQ
What is the maximum operating temperature range for STM32H573IIT3Q?
The STM32H573IIT3Q is rated for industrial temperature operation from –40°C to +105°C. This range is validated per JEDEC JESD22-A108 and applies to all specified electrical characteristics, including flash endurance (100K cycles at elevated temperature) and SRAM retention under thermal stress.
Does STM32H573IIT3Q support secure debug access after production lockdown?
Yes - secure debug remains available post-lockdown via authenticated SWD using a vendor-issued certificate chain. Debug access requires successful challenge-response authentication with the device's embedded secure element; unauthorized attempts trigger permanent debug disable and tamper flag assertion in backup registers.
How does the OTFDEC engine integrate with external Octo-SPI memories?
OTFDEC sits between the Octo-SPI controller and bus matrix, decrypting AES-128/256 ciphertext in real time during read transactions. It uses keys stored in secure SRAM or derived from HUK, with decryption occurring transparently to software - enabling execution from encrypted external flash without exposing plaintext in system memory.
Can the 640-Kbyte SRAM be configured with full ECC coverage across all regions?
No - ECC is selectively applied: SRAM2 (64 Kbyte) has fixed ECC; SRAM3 (320 Kbyte) supports flexible ECC granularity (per-word or per-block) via GTZC configuration; backup SRAM (4 Kbyte) and SRAM1 (256 Kbyte) lack ECC. Full ECC coverage requires explicit allocation to SRAM2/SRAM3 with appropriate GTZC settings.
STM32H573IIT3Q Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Package/Case:
- 176-LQFP
- Series:
- STM32H5
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- ARM® Cortex®-M33
- Core Size:
- 32-Bit
- Speed:
- 250MHz
- Connectivity:
- CANbus, Ethernet, I2C, IrDA, LINbus, MDIO, MMC/SD/SDIO, QSPI, SAI, SPDIF, SPI, UART/USART, USB OTG
- Peripherals:
- Brown-out Detect/Reset, DMA, I2S, PDR, POR, PWM, SHA, TRNG, Voltage Detect, WDT
- Number of I/O:
- 139
- Program Memory Size:
- 2MB (2M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 640K x 8
- Voltage - Supply (Vcc/Vdd):
- 1.71V ~ 3.6V
- Data Converters:
- A/D 20x12b SAR; D/A 2x12b
- Oscillator Type:
- External, Internal
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
STM32H573IIT3Q FAQ
1.How can I place an order for STM32H573IIT3Q through Aetrix?
Please submit a Request for Quotation (RFQ) for STM32H573IIT3Q on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for STM32H573IIT3Q reliable?
The price and inventory of STM32H573IIT3Q are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for STM32H573IIT3Q is usually 5 days.
3.What payment methods are accepted for STM32H573IIT3Q?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for STM32H573IIT3Q transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for STM32H573IIT3Q?
STM32H573IIT3Q orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your STM32H573IIT3Q order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for STM32H573IIT3Q?
For technical support, including STM32H573IIT3Q datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your STM32H573IIT3Q requirements.
6.How does Aetrix verify that STM32H573IIT3Q is sourced from the original manufacturer or authorized distributors?
All STM32H573IIT3Q products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that STM32H573IIT3Q meets industry standards.
7.What is the process for return or replacement of STM32H573IIT3Q?
All STM32H573IIT3Q units undergo pre-shipment inspection (PSI). If there is an issue with STM32H573IIT3Q, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The STM32H573IIT3Q part is unused and in its original packaging.
Return procedure for STM32H573IIT3Q:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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