STMicroelectronics STM32H573RIV6
- Part No.:
- STM32H573RIV6
- Manufacturer:
- STMicroelectronics
- Category:
- Microcontrollers
- Package:
- 68-VFQFN Exposed Pad
- Datasheet:
-
STM32H573RIV6.pdf
- Description:
- IC MCU 32BIT 2MB FLASH 68VFQFPN
- Quantity:
- Payment:

- Shipping:

Inventory:4,871
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
STM32H573RIV6 from STMicroelectronics is a high-security, high-performance Arm® Cortex®-M33 32-bit microcontroller with TrustZone®, FPU, and 250 MHz operation delivering 375 DMIPS. It integrates 2-Mbyte ECC-protected flash (dual-bank read-while-write), 640-Kbyte SRAM (including 64-Kbyte SRAM2 with ECC), and hardware cryptographic accelerators (AES, PKA, HASH, OTFDEC). It targets secure industrial control, IoT edge nodes, and trusted firmware execution environments.
For engineers reviewing the STM32H573RIV6 datasheet, STM32H573RIV6 pinout, STM32H573RIV6 application, or STM32H573RIV6 equivalent, key selection criteria include TrustZone-enforced peripheral isolation, dual-bank flash for robust OTA updates, on-the-fly Octo-SPI decryption, PSA Level 3/SESIP3 certification, and support for secure boot via ST-iROT and HUK-based key derivation.
Technical Context
The device implements Armv8-M mainline security with configurable SAU regions and GTZC-managed memory/peripheral protection. Its dual GPDMA controllers offload CPU during concurrent crypto operations and peripheral transfers, while CORDIC and FMAC coprocessors accelerate real-time signal processing without FPU saturation.
TrustZone-aware clock/reset management (RCC), power domain isolation (PWR), and secure debug authentication ensure end-to-end system integrity. The ART Accelerator includes 8-Kbyte instruction cache and 4-Kbyte data cache-enabling zero-wait-state execution from flash and external memories while maintaining deterministic timing in safety-critical contexts.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | Arm Cortex-M33 with TrustZone, FPU, MPU, up to 250 MHz - enables secure, deterministic real-time control with hardware-enforced privilege separation. |
| Flash Memory | 2 Mbytes with ECC, dual-bank RWW - supports atomic firmware updates and secure code/data partitioning across banks. |
| SRAM | 640 Kbytes total: 64-Kbyte SRAM2 (ECC), 320-Kbyte SRAM3 (flexible ECC), 4-Kbyte backup SRAM - ensures data retention in lowest power modes and fault-tolerant operation. |
| Crypto Acceleration | Dual AES coprocessors (one DPA-resistant), PKA, HASH, OTFDEC, TRNG (NIST SP800-90B) - enables fast, side-channel-resistant TLS handshake and secure boot verification. |
| Security Certification | PSA Certified Level 3 and SESIP3 assurance target - validates resistance against physical, fault injection, and software-based attacks per industry-standard threat models. |
| Interface Count | Up to 34 communication interfaces including 2× FDCAN, 12× U(S)ART, 6× SPI, 4× I²C, 2× SAI, Ethernet MAC, USB FS, UCPD - supports complex multi-protocol industrial gateways and edge AI inference pipelines. |
| Timers | 24 timers: 18× 16-bit (6 low-power), 2× 32-bit with quadrature encoder input, 2× watchdogs - delivers precise motor control, sensor synchronization, and fail-safe timeout monitoring. |
Pinout & Package
LQFP64 (10 × 10 mm) package with 64 pins; RoHS-compliant ECOPACK2 finish; thermal pad exposed on underside for enhanced heat dissipation in continuous 250 MHz operation.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD, VDDA, VDDIO2 | Power supply inputs | Separate domains for digital core (1.71–3.6 V), analog (1.71–3.6 V), and I/O (1.08–3.6 V) enable mixed-signal noise isolation and flexible voltage scaling. |
| NRST | Active-low reset input | Asynchronous reset with internal pull-up; supports external reset supervision and tamper-triggered secure wipe sequences. |
| BOOT0 | Boot mode selection | Configures primary boot source (system memory, flash, or embedded SRAM); behavior modified by TrustZone enable state (TZEN). |
| PA0–PA15, PB0–PB15, etc. | General-purpose I/Os | Up to 140 fast I/Os; most 5 V-tolerant; ten support independent 1.08 V supply - allows direct interfacing with legacy peripherals and ultra-low-voltage sensors. |
| PC13–PC15 | RTC/LSE interface | Dedicated pins for 32.768 kHz crystal or oscillator; supports VBAT-powered RTC and 32 backup registers in Standby mode. |
| PF0–PF15 | Octo-SPI interface | Supports x1/x2/x4/x8 serial protocols with on-the-fly decryption - enables secure boot from external encrypted PSRAM/NOR/HyperFlash without host CPU involvement. |
Key Features
| Feature | Design Value |
|---|---|
| Preconfigured immutable root of trust (ST-iROT) | Hardware-enforced boot entry point with secure hide protection area (HDP) prevents unauthorized firmware modification at power-on. |
| Secure firmware installation (SFI) | Enables authenticated, encrypted firmware loading via USB or UART using TF-M-compliant update mechanisms. |
| Flexible life cycle scheme | Four-stage device lifecycle (Development → Secure Development → Production → Locked) with irreversible transitions and secure debug authentication. |
| On-the-fly Octo-SPI decryption (OTFDEC) | Decrypts external memory contents in real time using AES-128/256 keys derived from hardware unique key (HUK), eliminating RAM exposure of plaintext code. |
| Two dual-port DMA controllers | Enable concurrent crypto engine transfers and peripheral data movement without CPU intervention - critical for deterministic real-time response under load. |
Applications
| Industrial PLC Controller | Secure IoT Edge Gateway |
|---|---|
Use Scenario: Programmable logic controller executing deterministic ladder logic and motion control loops in factory automation. IC Role / Device Role / Timing Role: Real-time control unit with dual 32-bit timers for quadrature encoder input, 6 low-power 16-bit timers for sensor polling, and FDCAN for fieldbus communication. Use Value: TrustZone isolates control firmware from communication stacks; dual-bank flash enables seamless firmware updates without stopping I/O scanning cycles. | Use Scenario: Cellular-connected gateway aggregating BLE/Zigbee sensor data, performing local AI inference, and forwarding to cloud via TLS-secured Ethernet/USB. IC Role / Device Role / Timing Role: Secure application processor with hardware-accelerated TLS handshake (PKA + AES), OTFDEC for encrypted model storage, and 12× U(S)ART for multi-protocol radio interfacing. Use Value: PSA Level 3 certification validates resistance to fault injection during secure boot; HUK-derived keys protect model weights and credentials at rest and in transit. |
| Medical Diagnostic Device | Smart Energy Meter |
Use Scenario: Portable ultrasound or ECG analyzer requiring FDA-grade firmware integrity, analog signal fidelity, and tamper-evident logging. IC Role / Device Role / Timing Role: Signal acquisition and processing hub with two 12-bit ADCs (5 Msps), DAC for calibration output, and digital temperature sensor for thermal drift compensation. Use Value: ECC-protected SRAM2 ensures reliable waveform buffer storage; active tampers trigger immediate secure erase of patient data upon enclosure breach. | Use Scenario: Revenue-grade electricity meter with metrology SoC interface, secure firmware updates, and anti-tampering detection for utility billing compliance. IC Role / Device Role / Timing Role: Trusted execution environment managing metrology data signing, secure time-stamping (RTC + VBAT), and encrypted communication with HAN/WAN modules. Use Value: SESIP3 certification meets IEC 62443-3-3 requirements; 96-bit unique ID enables cryptographic binding of firmware to hardware identity for remote attestation. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar high-security MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| STM32H753VIT6 | Arm Cortex-M7, no TrustZone, 480 MHz, 2-Mbyte flash, no PSA/SESIP certification, single AES accelerator | Lacks hardware-enforced security partitioning; suitable for performance-first non-certified applications | Select when maximum raw throughput is prioritized over certified security and secure boot enforcement. |
| NXP i.MX RT1176AVM8B | Arm Cortex-M7 + Cortex-M4 dual-core, 1 GHz, 2-Mbyte on-chip RAM, EdgeLock SE050 secure element co-processor | Relies on discrete secure element for root of trust; higher power and BOM cost than integrated TrustZone solution | Select when heterogeneous dual-core processing (e.g., M7 for AI, M4 for real-time control) justifies added complexity and cost. |
Compared with STM32H573RIV6, the STM32H753VIT6 trades certified security for higher clock speed and lacks on-the-fly external memory decryption, while the i.MX RT1176 requires external secure element integration to match PSA Level 3 assurance - making the H573 the only single-die, pre-certified solution for compact, cost-sensitive secure edge devices.
Availability
STM32H573RIV6 is available at Aetrix Electronics and suitable for industrial PLC controllers, secure IoT edge gateways, medical diagnostic devices, and smart energy meters requiring stable component supply across long product lifecycles.
Supply support for STM32H573RIV6 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power management ICs, sensors, and automotive semiconductors since 1987.
The STM32H5 series is ST's flagship high-security MCU line targeting PSA-certified applications in industrial, healthcare, and infrastructure markets - built around Arm Cortex-M33 with hardened TrustZone and integrated cryptographic engines.
FAQ
What is the maximum operating frequency and corresponding DMIPS rating?
The STM32H573RIV6 operates at up to 250 MHz and delivers 375 DMIPS (Dhrystone 2.1), measured with the ART Accelerator enabled and instruction cache active. This performance level is sustained across temperature ranges (-40°C to +125°C) and supply voltages (1.71–3.6 V), verified per DS14121 Rev 5 electrical characteristics section 5.3.1.
Does this part support secure boot from external memory?
Yes - the STM32H573RIV6 supports secure boot from external Octo-SPI memories using its on-the-fly decryption engine (OTFDEC). Decryption uses AES-128/256 keys derived from the hardware unique key (HUK), and the decrypted code executes directly from external memory without exposing plaintext in internal SRAM.
How many independent power domains does the device support for low-power operation?
The device supports three independent power domains: VDD (core/digital), VDDA (analog), and VDDIO2 (I/O), each with configurable voltage scaling. In Stop mode, SRAM2 and backup registers remain powered via VBAT, enabling wake-up from RTC alarm or tamper event while consuming ≤1.5 µA - specified in DS14121 section 5.3.7.
Is the LQFP64 package pin-compatible with other STM32H573 variants?
No - the STM32H573RIV6 uses the LQFP64 (10 × 10 mm) package with specific pin mapping defined in DS14121 section 4.1. Other variants like STM32H573VIH6 use UFBGA176+25, and STM32H573ZIT6 uses LQFP144; pinouts differ significantly due to peripheral count and routing constraints across packages.
STM32H573RIV6 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Package/Case:
- 68-VFQFN Exposed Pad
- Series:
- STM32H5
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- ARM® Cortex®-M33
- Core Size:
- 32-Bit
- Speed:
- 250MHz
- Connectivity:
- CANbus, Ethernet, I2C, IrDA, LINbus, MDIO, MMC/SD/SDIO, QSPI, SAI, SPDIF, SPI, UART/USART, USB OTG
- Peripherals:
- Brown-out Detect/Reset, DMA, I2S, PDR, POR, PWM, SHA, TRNG, Voltage Detect, WDT
- Number of I/O:
- 53
- Program Memory Size:
- 2MB (2M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 640K x 8
- Voltage - Supply (Vcc/Vdd):
- 1.71V ~ 3.6V
- Data Converters:
- A/D 16x12b SAR; D/A 2x12b
- Oscillator Type:
- External, Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
STM32H573RIV6 FAQ
1.How can I place an order for STM32H573RIV6 through Aetrix?
Please submit a Request for Quotation (RFQ) for STM32H573RIV6 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for STM32H573RIV6 reliable?
The price and inventory of STM32H573RIV6 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for STM32H573RIV6 is usually 5 days.
3.What payment methods are accepted for STM32H573RIV6?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for STM32H573RIV6 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for STM32H573RIV6?
STM32H573RIV6 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your STM32H573RIV6 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for STM32H573RIV6?
For technical support, including STM32H573RIV6 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your STM32H573RIV6 requirements.
6.How does Aetrix verify that STM32H573RIV6 is sourced from the original manufacturer or authorized distributors?
All STM32H573RIV6 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that STM32H573RIV6 meets industry standards.
7.What is the process for return or replacement of STM32H573RIV6?
All STM32H573RIV6 units undergo pre-shipment inspection (PSI). If there is an issue with STM32H573RIV6, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The STM32H573RIV6 part is unused and in its original packaging.
Return procedure for STM32H573RIV6:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
STM32H573RIV6 Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

