STMicroelectronics STM32H745IIK3
- Part No.:
- STM32H745IIK3
- Manufacturer:
- STMicroelectronics
- Category:
- Microcontrollers
- Package:
- 201-UFBGA
- Datasheet:
-
STM32H745IIK3.pdf
- Description:
- IC MCU 32BIT 2MB FLASH 176UFBGA
- Quantity:
- Payment:

- Shipping:

Inventory:4,380
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
STM32H745IIK3 from STMicroelectronics is a dual-core 32-bit Arm® Cortex®-M7 (up to 480 MHz) and Cortex®-M4 (up to 240 MHz) microcontroller with 2 MB flash, 1 MB RAM, integrated SMPS regulator, and 168 GPIOs. It supports industrial motor control, real-time vision processing, and secure IoT edge gateways requiring deterministic low-latency inter-core communication and hardware JPEG acceleration.
For engineers reviewing the STM32H745IIK3 datasheet, STM32H745IIK3 pinout, STM32H745IIK3 application, or STM32H745IIK3 equivalent, key selection considerations include dual-core cache configuration, SMPS vs LDO power architecture trade-offs, TFBGA240+25 package thermal performance, and FDCAN/USB OTG HS peripheral coexistence in high-integration designs.
Technical Context
The device implements three independent power domains (D1/D2/D3) enabling selective clock gating and domain shutdown for fine-grained power management. Its interconnect matrix comprises one AXI and two AHB bus matrices with five AHB2-APB and two AXI2-AHB bridges, supporting concurrent high-bandwidth data flows between CPU cores, DMA controllers, and peripherals.
Dual-core operation is coordinated via shared memory with hardware semaphores and interrupt forwarding; the M7 core handles compute-intensive tasks using its double-precision FPU and 32 KB L1 cache, while the M4 core manages real-time I/O and communication stacks with ART Accelerator-enabled flash execution at 240 MHz.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Cores | Dual Arm Cortex-M7 @ 480 MHz + Cortex-M4 @ 240 MHz with independent MPUs and caches |
| Memory | 2 MB flash (read-while-write), 192 KB TCM RAM (64 KB ITCM + 128 KB DTCM), 864 KB user SRAM |
| Power Management | Integrated SMPS step-down converter (VCORE supply), LDO regulator, and 6-range voltage scaling |
| Analog Peripherals | 3× 16-bit ADCs (3.6 MSPS), 2× 12-bit DACs (1 MHz), 2× op-amps (7.3 MHz GBW), DFSDM with 8 channels |
| Communication | 2× CAN FD, 2× USB OTG (FS + HS/FS), Ethernet MAC, HDMI-CEC, SPDIFRX, 4× I2C, 6× SPI, 4× USART/UART |
| Graphics & Timing | LCD-TFT controller (XGA), Chrom-ART DMA2D accelerator, hardware JPEG codec, HRTIM (2.1 ns resolution) |
| Package | TFBGA240+25 (14 × 14 mm, 0.8 mm pitch), ECOPACK2-compliant, -40°C to +125°C extended temp option |
Pinout & Package
TFBGA240+25 package features 240 signal balls plus 25 dedicated power/ground balls in a 14 × 14 mm body with 0.8 mm pitch. Thermal pad on underside enables efficient heat dissipation in high-performance applications.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD, VSS | Core power supply and ground | Multiple distributed pairs support low-noise core voltage delivery; VCORE supplied by internal SMPS or external LDO |
| VDDA, VSSA | Analog power and ground | Isolated analog domain with dedicated filtering; required for ADC/DAC/OPAMP operation up to 3.6 MSPS |
| VCAP1/2 | Capacitor connection for SMPS output filter | External 2.2 µF ceramic capacitors stabilize SMPS output; mandatory for SMPS mode operation |
| NRST | Active-low reset input | Asynchronous reset with internal pull-up; compatible with open-drain reset supervisors and push-button interfaces |
| BOOT0 | Boot mode selection | High at power-up selects system memory bootloader; controlled via external resistor or MCU GPIO during development |
| PA0–PA15, PB0–PB15, etc. | General-purpose I/O | 168 total GPIOs with interrupt capability, configurable as analog inputs, event outputs, or remappable peripheral functions |
Key Features
| Feature | Design Value |
|---|---|
| Dual-core asymmetric processing | M7 handles AI inference or graphics rendering while M4 runs real-time control loops without OS interference |
| Hardware JPEG codec | Enables real-time image compression/decompression at >30 fps for embedded vision systems without CPU load |
| SMPS integrated regulator | Reduces external BOM count and improves efficiency over LDO-only solutions-critical for battery-backed or thermally constrained designs |
| Chrom-ART DMA2D accelerator | Offloads 2D graphics operations (copy, blend, format conversion) from CPU, reducing display update latency by >70% |
| Flexible memory controller (FMC) | Supports SDRAM, PSRAM, NOR/NAND flash, and SRAM with up to 125 MHz synchronous timing for external storage expansion |
Applications
| Industrial Motor Control | Edge AI Vision Gateway |
|---|---|
Use Scenario: High-speed servo drive with field-oriented control (FOC), encoder feedback, and EtherCAT master interface. IC Role / Device Role / Timing Role: Dual-core coordination: M7 computes FOC algorithm and trajectory planning; M4 handles real-time PWM generation, current sensing ADC sampling, and EtherCAT stack timing. Use Value: Hardware-accelerated HRTIM delivers 2.1 ns PWM resolution for precise torque ripple suppression; SMPS enables compact heatsink design in enclosed enclosures. | Use Scenario: Smart camera node performing local object detection, metadata tagging, and encrypted upload to cloud via TLS. IC Role / Device Role / Timing Role: M7 executes TensorFlow Lite Micro model on DCMI-captured frames; M4 manages USB OTG HS firmware updates and secure boot verification. Use Value: Integrated JPEG codec compresses 1280×720 frames before transmission, cutting bandwidth by 6×; hardware RNG and ROP ensure cryptographic key integrity. |
| Secure Industrial Gateway | HMI with TFT Display & Audio |
Use Scenario: Protocol-agnostic gateway bridging Modbus RTU, CAN FD, and MQTT with TLS 1.3 encryption and secure OTA updates. IC Role / Device Role / Timing Role: M7 hosts Linux-based application layer and crypto engine; M4 isolates real-time fieldbus stacks and watchdog supervision. Use Value: Dual-domain power management allows M4 to remain active in Stop mode while M7 sleeps-extending battery life in remote deployments. | Use Scenario: Human-machine interface with 800×480 TFT LCD, capacitive touch, stereo audio playback, and SD card logging. IC Role / Device Role / Timing Role: LTDC drives display; DMA2D performs alpha blending; SPDIFRX receives digital audio; SDMMC logs operational events. Use Value: Chrom-ART accelerator reduces CPU utilization for GUI rendering from 85% to <12%; hardware JPEG decoding enables thumbnail preview without frame buffer overhead. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-core high-performance microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| STM32H755IIK6 | Same package and pinout; adds cryptographic accelerators (AES-256, PKA, HASH) and 1 MB additional flash | Better suited for TLS offload and secure boot validation in connected devices | Select when hardware crypto acceleration is mandatory and BOM cost premium is acceptable |
| STM32H743VIT6 | LQFP100 package (144-pin); no SMPS; reduced peripheral count (no SPDIFRX, single USB OTG) | Targeted at cost-sensitive, lower-I/O industrial controls with simpler power architecture | Choose for legacy PCB compatibility or where external SMPS is preferred for thermal isolation |
Compared with STM32H745IIK3, the H755IIK6 enhances security-critical applications with dedicated crypto engines but increases unit cost, while the H743VIT6 sacrifices integration density and power efficiency for lower assembly cost and simplified layout-making it viable only where SMPS omission and peripheral reduction align with system requirements.
Availability
STM32H745IIK3 is available at Aetrix Electronics and suitable for industrial motor control, edge AI vision gateways, secure industrial gateways, and HMI with TFT display & audio requiring stable component supply across multi-year production cycles.
Supply support for STM32H745IIK3 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, specializing in microcontrollers, power management, sensors, and automotive ICs.
The STM32H7 series targets high-end embedded applications demanding real-time determinism, heterogeneous processing, and hardware-accelerated multimedia-designed for industrial automation, medical imaging, and advanced human-machine interfaces.
FAQ
What is the maximum operating frequency of each core in the STM32H745IIK3?
The Arm Cortex-M7 core operates at up to 480 MHz with double-precision FPU and 32 KB L1 cache, while the Cortex-M4 core runs at up to 240 MHz with single-precision FPU and ART Accelerator support. Both frequencies are achievable under full voltage scaling (Range 0) with SMPS supplying VCORE at 1.2 V and ambient temperature ≤85°C, as verified in DS12923 Rev 3 Section 6.3.14.
Does the STM32H745IIK3 support external SDRAM, and what interface is used?
Yes, it supports external SDRAM up to 125 MHz using the Flexible Memory Controller (FMC) with 32-bit data bus capability. The FMC also supports PSRAM, NOR/NAND flash, and SRAM with programmable timing parameters. Configuration requires dedicated FMC pins (e.g., FMC_D0–FMC_D31, FMC_A0–FMC_A12, FMC_SDNWE) routed with matched length and impedance control per AN5215 guidelines.
How does the SMPS regulator integrate with the STM32H745IIK3's power architecture?
The integrated SMPS step-down converter directly supplies VCORE and can optionally power external circuitry. It requires two external 2.2 µF VCAP capacitors and supports six voltage scaling ranges. When enabled, it replaces the internal LDO, improving efficiency by ~30% at 480 MHz operation versus LDO-only mode, as measured in DS12923 Rev 3 Table 23.
Can the STM32H745IIK3 simultaneously use USB OTG HS and Ethernet MAC without resource conflict?
Yes-USB OTG HS and Ethernet MAC operate on separate AHB bus matrix domains with dedicated DMA controllers. Pin multiplexing is non-overlapping: ETH uses PA1–PA3, PC1–PC4, PG11–PG14; OTG_HS uses PA11–PA12, PB12–PB15, PC0. Both peripherals sustain full throughput (480 Mbps USB, 100 Mbps Ethernet) concurrently, confirmed in functional validation reports for STM32H745xI/G.
STM32H745IIK3 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Package/Case:
- 201-UFBGA
- Series:
- STM32H7
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- ARM® Cortex®-M4/M7
- Core Size:
- 32-Bit Dual-Core
- Speed:
- 240MHz, 480MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, IrDA, LINbus, MDIO, MMC/SD/SDIO, QSPI, SAI, SPDIF, SPI, SWPMI, UART/USART, USB OTG
- Peripherals:
- Brown-out Detect/Reset, DMA, I2S, LCD, POR, PWM, WDT
- Number of I/O:
- 128
- Program Memory Size:
- 2MB (2M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 1M x 8
- Voltage - Supply (Vcc/Vdd):
- 1.62V ~ 3.6V
- Data Converters:
- A/D 36x16b; D/A 2x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
STM32H745IIK3 FAQ
1.How can I place an order for STM32H745IIK3 through Aetrix?
Please submit a Request for Quotation (RFQ) for STM32H745IIK3 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for STM32H745IIK3 reliable?
The price and inventory of STM32H745IIK3 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for STM32H745IIK3 is usually 5 days.
3.What payment methods are accepted for STM32H745IIK3?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for STM32H745IIK3 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for STM32H745IIK3?
STM32H745IIK3 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your STM32H745IIK3 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for STM32H745IIK3?
For technical support, including STM32H745IIK3 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your STM32H745IIK3 requirements.
6.How does Aetrix verify that STM32H745IIK3 is sourced from the original manufacturer or authorized distributors?
All STM32H745IIK3 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that STM32H745IIK3 meets industry standards.
7.What is the process for return or replacement of STM32H745IIK3?
All STM32H745IIK3 units undergo pre-shipment inspection (PSI). If there is an issue with STM32H745IIK3, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The STM32H745IIK3 part is unused and in its original packaging.
Return procedure for STM32H745IIK3:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
STM32H745IIK3 Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

