My Inquiry
My Account
STMicroelectronics STM32H755XIH3TR
- Part No.:
- STM32H755XIH3TR
- Manufacturer:
- STMicroelectronics
- Category:
- Microcontrollers
- Package:
- 265-TFBGA
- Datasheet:
-
STM32H755XIH3TR.pdf
- Description:
- IC MCU 32BIT 2MB FLASH 265TFBGA
- Quantity:
- Payment:
- Shipping:
Inventory:4,141
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
STM32H755XIH3TR from STMicroelectronics is a dual-core Arm® Cortex®-M7 (480 MHz) and Cortex®-M4 (240 MHz) microcontroller with 2 MB flash, 1 MB RAM (192 KB TCM + 864 KB SRAM), integrated SMPS regulator, hardware crypto (AES-256, SHA-2, RNG), and 46 communication/analog interfaces. It targets high-performance industrial control, motor drives, and edge AI inference at the device level.
For engineers reviewing the STM32H755XIH3TR datasheet, STM32H755XIH3TR pinout, STM32H755XIH3TR application, or STM32H755XIH3TR equivalent, key selection criteria include dual-core real-time partitioning, on-chip SMPS efficiency (vs. external LDO), cryptographic acceleration latency, and TFBGA240+25 package I/O density for compact PCB layouts.
Technical Context
The device implements a three-domain power architecture (D1/D2/D3) enabling independent clock gating and voltage scaling across performance, peripheral, and system-control subsystems. Core isolation is enforced via separate MPUs, memory protection units, and dedicated bus matrices (AXI + dual AHB).
Its interconnect includes 4 DMA controllers - notably a high-speed MDMA with linked-list support - and dual-mode Quad-SPI running up to 133 MHz. Clock management uses three fractional PLLs: one for system clock, two for kernel clocks, supporting precise timing for USB HS, Ethernet, and audio applications.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Cores | Dual Arm® Cortex®-M7 @ 480 MHz (1027 DMIPS) + Cortex®-M4 @ 240 MHz (300 DMIPS); enables asymmetric RTOS or bare-metal + Linux offload. |
| Memory | 2 MB flash (read-while-write), 1 MB RAM (192 KB TCM + 864 KB SRAM + 4 KB backup); supports time-critical ISR in ITCM and large buffer handling in user SRAM. |
| Power Management | Integrated SMPS step-down converter (VCORE supply), LDO, and 6-range voltage scaling; reduces BOM cost and improves efficiency vs. discrete regulators. |
| Analog Peripherals | 3× 16-bit ADCs (3.6 MSPS), 2× 12-bit DACs (1 MHz), 2× op-amps (7.3 MHz GBW), DFSDM; suitable for closed-loop motor control and sensor fusion. |
| Communication | 2× CAN FD, 2× USB OTG (FS/HS), Ethernet MAC, SPDIFRX, HDMI-CEC, 8–14-bit DCMI; enables industrial gateway, vision-enabled HMI, and time-sensitive networking. |
| Crypto Acceleration | AES-128/192/256, TDES, HASH (SHA-1/SHA-2), HMAC, TRNG; accelerates secure boot, OTA firmware updates, and TLS handshake offload. |
| Package | TFBGA240+25 (14 × 14 mm, 0.8 mm pitch); provides 168 GPIOs with interrupt capability and high-density routing for complex mixed-signal designs. |
Pinout & Package
STM32H755XIH3TR is housed in a TFBGA240+25 package (14 × 14 mm, 0.8 mm ball pitch) with 240 signal balls plus 25 ground/power balls. The package supports ECOPACK2 environmental compliance and extended temperature operation up to 125 °C.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD, VSS | Core power supply / ground | Supplies VCORE domain (1.05–1.32 V); requires external VCAP capacitor for SMPS stability. |
| VDDA, VSSA | Analog power supply / ground | Isolated 3.3 V analog rail for ADC/DAC/OPAMP; minimizes digital noise coupling into precision analog paths. |
| NRST | Active-low reset input | Asynchronous reset with internal pull-up; compatible with external reset supervisors and push-button debouncing circuits. |
| BOOT0 | Boot mode selection | Configures boot source (system memory, embedded flash, or FMC); sampled at power-on reset only. |
| PA0–PA15, PB0–PB15, etc. | General-purpose I/O | 168 total GPIOs with interrupt capability, configurable as analog inputs, timers, or alternate-function peripherals (e.g., FMC, QUADSPI). |
Key Features
| Feature | Design Value |
|---|---|
| Dual-core asymmetric execution | M7 handles real-time deterministic tasks (motor control, graphics), M4 manages connectivity (USB, Ethernet, CAN FD) without OS interference. |
| ART Accelerator + L1 cache | Eliminates flash wait states for both cores; enables zero-wait-state execution at 480 MHz (M7) and 240 MHz (M4) from internal flash. |
| Flexible memory controller (FMC) | Supports SDRAM, PSRAM, NOR/NAND up to 125 MHz sync mode; enables external frame buffers for LCD-TFT or video streaming. |
| Chrom-ART Accelerator (DMA2D) | Hardware bitmap blending and image format conversion; reduces CPU load by >70% in GUI rendering for XGA-resolution displays. |
| Hardware JPEG codec | Real-time encode/decode of JPEG images up to 1080p; offloads image compression from CPU in camera or surveillance applications. |
Applications
| Industrial Motor Drive | Edge Vision Gateway |
|---|---|
|
Use Scenario: Field-oriented control (FOC) of 3-phase PMSM motors with real-time current sensing and PWM generation. IC Role / Device Role / Timing Role: Dual-core coordination: M7 executes FOC algorithm with 2.1 ns HRTIM resolution; M4 handles EtherCAT/PROFINET stack and diagnostics. Use Value: Sub-microsecond PWM synchronization and deterministic loop timing enable <1% torque ripple at 20 kHz switching frequency. |
Use Scenario: Multi-camera ingestion (up to 80 MHz DCMI), preprocessing, and encrypted upload to cloud via Ethernet/USB. IC Role / Device Role / Timing Role: M7 runs OpenCV kernels on DMA2D-accelerated frame buffers; M4 manages JPEG encoding, crypto, and network stack. Use Value: Hardware JPEG + AES-256 cuts end-to-end latency by 40% vs. software-only pipeline while meeting ISO/IEC 27001 data-at-rest requirements. |
| Secure HMI Controller | High-Performance PLC Base |
|
Use Scenario: Touch-enabled XGA TFT display with secure boot, OTA update, and tamper detection for medical equipment UI. IC Role / Device Role / Timing Role: M7 drives LTDC controller and Chrom-ART; M4 validates signed firmware images using HASH+RNG before flash write. Use Value: Active tamper detection + ROP/PC-ROP prevents physical firmware extraction; backup SRAM retains session keys during brownout. |
Use Scenario: Deterministic cyclic execution of IEC 61131-3 logic with sub-ms scan times and dual-CAN FD fieldbus interfacing. IC Role / Device Role / Timing Role: M7 runs real-time scheduler and motion control loops; M4 handles CAN FD messaging, SDMMC logging, and web server. Use Value: 6-range voltage scaling allows dynamic core frequency adjustment to maintain <500 µs cycle time under variable thermal load. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-core high-performance microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| STM32H743VIT6 | Single Cortex-M7 core (480 MHz), 2 MB flash, 1 MB RAM, no SMPS, LQFP100 package (144 pins) | Lacks dual-core isolation and integrated SMPS; lower I/O count and no CAN FD support | Select when cost-sensitive single-core deterministic control suffices and external regulator is acceptable. |
| NXP i.MX RT1176DVMAA | Arm Cortex-M7 (1 GHz) + M4 (400 MHz), 2 MB SRAM, no on-chip flash, no SMPS, 289-pin BGA | Requires external flash; lacks hardware JPEG, DFSDM, and analog peripherals; higher peak power draw | Select for ultra-high compute throughput where external memory bandwidth outweighs integrated analog feature needs. |
Compared with STM32H743VIT6, the STM32H755XIH3TR adds dual-core security partitioning and SMPS efficiency; versus i.MX RT1176DVMAA, it delivers tighter analog integration and lower BOM count for sensor-rich industrial edge nodes.
Availability
STM32H755XIH3TR is available at Aetrix Electronics and suitable for industrial motor drives, edge vision gateways, secure HMIs, and high-performance PLC bases requiring stable component supply across multi-year production cycles.
Supply support for STM32H755XIH3TR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, specializing in microcontrollers, power management, sensors, and automotive ICs with strong industrial and automotive focus.
This part belongs to the STM32H7 series, designed for high-end real-time embedded applications demanding dual-core processing, advanced security, and rich analog/multimedia peripherals in a single chip.
FAQ
What is the maximum operating temperature range for STM32H755XIH3TR?
The STM32H755XIH3TR is rated for industrial operation from –40 °C to +85 °C. An extended temperature variant (e.g., STM32H755XIH3TR-Y) supports up to +125 °C, verified per ST's ECOPACK2 qualification and thermal derating curves in Section 7.7 of DS12919 Rev 3.
Does STM32H755XIH3TR support hardware-based secure boot?
Yes. It implements secure boot via ROM-based bootloader with Root-of-Trust (RoT) verification using embedded public key cryptography, ROP/PC-ROP protection, and active tamper detection on VDD/VSS/RTC pins - all documented in Sections 3.3.2 and 9 of DS12919 Rev 3.
Can the SMPS regulator supply external circuitry?
Yes. The integrated SMPS can directly supply both VCORE and external components (e.g., DDR memory, analog front-ends) with output current up to 1.2 A, as specified in Tables 16–17 of DS12919 Rev 3, provided external inductor/capacitor values meet recommended values.
How many independent ADC instances does STM32H755XIH3TR provide?
It integrates three independent 16-bit ADCs (ADC1–ADC3), each supporting up to 16 channels, simultaneous sampling, and hardware oversampling - confirmed in Section 3.17 and Table 21 of DS12919 Rev 3, with max aggregate throughput of 3.6 MSPS.
STM32H755XIH3TR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Package/Case:
- 265-TFBGA
- Series:
- STM32H7
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- ARM® Cortex®-M4, Cortex®-M7
- Core Size:
- 32-Bit Dual-Core
- Speed:
- 240MHz, 480MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, IrDA, LINbus, MDIO, MMC/SD/SDIO, QSPI, SAI, SPDIF, SPI, SWPMI, UART/USART, USB OTG
- Peripherals:
- Brown-out Detect/Reset, DMA, I2S, LCD, POR, PWM, WDT
- Number of I/O:
- 168
- Program Memory Size:
- 2MB (2M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 1M x 8
- Voltage - Supply (Vcc/Vdd):
- 1.62V ~ 3.6V
- Data Converters:
- A/D 36x16b; D/A 2x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
STM32H755XIH3TR FAQ
1.How can I place an order for STM32H755XIH3TR through Aetrix?
Please submit a Request for Quotation (RFQ) for STM32H755XIH3TR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for STM32H755XIH3TR reliable?
The price and inventory of STM32H755XIH3TR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for STM32H755XIH3TR is usually 5 days.
3.What payment methods are accepted for STM32H755XIH3TR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for STM32H755XIH3TR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for STM32H755XIH3TR?
STM32H755XIH3TR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your STM32H755XIH3TR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for STM32H755XIH3TR?
For technical support, including STM32H755XIH3TR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your STM32H755XIH3TR requirements.
6.How does Aetrix verify that STM32H755XIH3TR is sourced from the original manufacturer or authorized distributors?
All STM32H755XIH3TR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that STM32H755XIH3TR meets industry standards.
7.What is the process for return or replacement of STM32H755XIH3TR?
All STM32H755XIH3TR units undergo pre-shipment inspection (PSI). If there is an issue with STM32H755XIH3TR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The STM32H755XIH3TR part is unused and in its original packaging.
Return procedure for STM32H755XIH3TR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
STM32H755XIH3TR Tags
-
ATTINY4-TSHR
Microchip Technology
-
ATTINY10-TSHR
Microchip Technology
-
ATTINY10-TS8R
Microchip Technology
-
ATTINY202-SSNR
Microchip Technology
-
ATTINY202-SSFR
Microchip Technology
-
ATTINY402-SSNR
Microchip Technology
-
PIC16F15213T-I/MF
Microchip Technology
-
PIC16F15213-E/MF
Microchip Technology
-
PIC10F200T-I/OT
Microchip Technology
-
ATTINY412-SSNR
Microchip Technology
-
PIC10F202T-I/OT
Microchip Technology
-
ATTINY404-SSNR
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
