STMicroelectronics STM32H755XIH6
- Part No.:
- STM32H755XIH6
- Manufacturer:
- STMicroelectronics
- Category:
- Microcontrollers
- Package:
- 265-TFBGA
- Datasheet:
-
STM32H755XIH6.pdf
- Description:
- IC MCU 32BIT 2MB FLASH 265TFBGA
- Quantity:
- Payment:

- Shipping:

Inventory:977
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
STM32H755XIH6 from STMicroelectronics is a dual-core 32-bit Arm® Cortex®-M7 (up to 480 MHz) and Cortex®-M4 (up to 240 MHz) microcontroller with 2 MB flash, 1 MB RAM (including 192 KB TCM), integrated SMPS regulator, hardware crypto acceleration (AES-256, SHA-2, RNG), and 46 communication/analog peripherals. It targets high-performance industrial control, motor drives, and real-time edge AI inference at the device level.
For engineers reviewing the STM32H755XIH6 datasheet, STM32H755XIH6 pinout, STM32H755XIH6 application, or STM32H755XIH6 equivalent, key selection considerations include dual-core deterministic timing, on-chip SMPS for power efficiency, hardware JPEG/DFSDM support for vision/audio preprocessing, and secure firmware upgrade capability in production systems.
Technical Context
The device implements a hierarchical power domain architecture (D1/D2/D3) enabling independent clock gating and voltage scaling across performance, peripheral, and system-control subsystems. Its interconnect matrix comprises one AXI and two AHB bus matrices with five AHB2-APB and two AXI2-AHB bridges, supporting concurrent high-bandwidth data flows between CPU cores, DMA controllers (MDMA + dual-port DMAs), and peripherals.
Dual-core operation is coordinated via shared memory, semaphores, and interrupt forwarding through the NVIC; the M7 core handles time-critical tasks using ITCM/DTCM RAM and L1 cache (16 KB I-cache + 16 KB D-cache), while the M4 core manages communication stacks and real-time control loops with ART Accelerator-optimized flash execution.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Cores | Dual Arm® Cortex®-M7 @ 480 MHz (1027 DMIPS) + Cortex®-M4 @ 240 MHz (300 DMIPS); enables asymmetric task partitioning with hardware isolation. |
| Memory | 2 MB flash (read-while-write), 1 MB RAM (192 KB TCM + 864 KB SRAM + 4 KB backup); supports zero-wait-state execution and deterministic latency-critical routines. |
| Power Management | Integrated SMPS step-down converter + LDO; enables direct VCORE supply with 6 voltage scaling ranges and 2.95 µA standby current (RTC/LSE active). |
| Analog Peripherals | 3× 16-bit ADCs (3.6 MSPS), 2× 12-bit DACs (1 MHz), 2× op-amps (7.3 MHz GBW), DFSDM (8-channel sigma-delta filtering); suitable for precision sensor fusion and closed-loop analog control. |
| Communication Interfaces | 2× CAN FD + 1× TT-CAN, 4× USART/UART + 1× LPUART, 4× I2C FM+, 6× SPI (incl. Quad-SPI @ 133 MHz), Ethernet MAC, USB OTG HS/FS, HDMI-CEC; meets industrial fieldbus and connectivity requirements. |
| Crypto & Security | AES-128/192/256, TDES, HASH (SHA-1/SHA-2), HMAC, true RNG, ROP/PC-ROP, active tamper detection; enables secure boot, OTA updates, and data confidentiality in connected devices. |
Pinout & Package
STM32H755XIH6 uses a TFBGA240+25 package (14 × 14 mm, 0.8 mm pitch) with 240 signal balls plus 25 dedicated power/ground balls. Pin functions are defined per ball position in ST's official pinout table (DS12919 Rev 3, Section 5), including dual-core debug (SWD/JTAG), multiple VDD/VSS groups per domain, and dedicated SMPS feedback/control pins (VSENSE, FB, COMP).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDDA/VSSA | Analog power supply/ground | Isolated 1.62–3.6 V supply for ADC/DAC/OPAMP; requires separate filtering to maintain 16-bit conversion accuracy. |
| VCAP1/VCAP2 | Core voltage decoupling | Connects to external 2.2 µF ceramic capacitors for stable 1.1 V core rail; mandatory for SMPS or LDO operation. |
| BOOT0 | Boot mode selection | High at reset selects system memory bootloader; used for field firmware recovery without debugger. |
| NRST | Asynchronous reset input | Active-low pin with internal pull-up; triggers full system reset including both CPU cores and peripherals. |
| PA13/PA14 | SWD debug interface | Serial Wire Debug clock/data; enables single-pin debug access (SWDIO/SWCLK) for development and production programming. |
Key Features
| Feature | Design Value |
|---|---|
| Dual-core deterministic execution | Independent cache, TCM, and power domains allow M7 to run real-time control loops at 480 MHz while M4 handles protocol stacks-no resource contention. |
| Hardware JPEG codec | Accelerates encode/decode of YUV422/JPEG streams up to XGA resolution; offloads CPU by >90% in camera-based HMI or surveillance nodes. |
| Chrom-ART DMA2D accelerator | Performs 2D graphics operations (copy, blend, format conversion) without CPU involvement; reduces frame buffer update latency in TFT-LCD applications. |
| DFSDM with 8 channels | Digitizes sigma-delta modulator outputs (e.g., MEMS microphones, current sensors) with configurable filters and oversampling-enables high-precision audio/sensor acquisition. |
| SMPS + LDO co-regulation | Switch-mode supply drives VCORE efficiently; LDO powers I/Os and analog blocks-achieves 2.95 µA standby while retaining RTC, backup SRAM, and LSE. |
Applications
| Industrial PLC Controller | Edge AI Vision Node |
|---|---|
Use Scenario: Real-time motion control with multi-axis servo coordination and EtherCAT fieldbus communication. IC Role / Device Role / Timing Role: Dual-core orchestrates deterministic servo loop (M7 @ 480 MHz) and EtherCAT stack (M4 @ 240 MHz) with sub-microsecond jitter via shared memory and hardware semaphores. Use Value: Eliminates external FPGA or dual-MCU architecture; reduces BOM cost by 35% while meeting IEC 61131-3 cycle time < 100 µs. | Use Scenario: Low-power smart camera for defect detection on factory lines using CNN inference on captured images. IC Role / Device Role / Timing Role: M7 runs TensorFlow Lite Micro inference engine; M4 pre-processes raw sensor data via DFSDM and JPEG codec before feeding to M7. Use Value: Hardware JPEG compression cuts image transfer bandwidth by 8×; on-chip crypto secures model updates over MQTT/TLS. |
| Secure Gateway Device | High-Fidelity Audio Processor |
Use Scenario: Field gateway aggregating Modbus RTU, CAN FD, and BLE data with TLS-secured cloud upload. IC Role / Device Role / Timing Role: M4 handles protocol translation and BLE stack; M7 manages TLS handshake, AES encryption, and secure OTA validation using embedded keys. Use Value: ROP/PC-ROP and active tamper detection prevent physical firmware extraction; secure boot ensures only signed images execute. | Use Scenario: Professional audio mixer with 8-channel MEMS microphone array and real-time noise suppression. IC Role / Device Role / Timing Role: DFSDM digitizes sigma-delta outputs; M7 applies adaptive filtering and beamforming algorithms; Chrom-ART renders UI on TFT display. Use Value: 16-bit ADCs with 3.6 MSPS sample rate capture full audio bandwidth; op-amps condition analog inputs with 7.3 MHz GBW for low-distortion front-end. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-core high-performance microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| STM32H743VIT6 | Same dual-core architecture but 1 MB flash, no SMPS, 144-pin LQFP package; lacks hardware JPEG and DFSDM. | Suitable for cost-sensitive motor control where JPEG/DFSDM not required; lower pin count simplifies PCB layout. | Select when power efficiency and advanced analog/audio features are secondary to BOM cost and design simplicity. |
| NXP i.MX RT1176DVMAA | Arm Cortex-M7 @ 1 GHz + M4 @ 400 MHz; 2 MB on-chip RAM but no embedded flash; external QSPI required; no SMPS or hardware JPEG. | Better raw compute for ML inference, but higher external memory dependency and no integrated power regulation. | Prefer for ultra-high-throughput edge AI where external memory bandwidth outweighs power/size constraints. |
Compared with STM32H743VIT6, the STM32H755XIH6 adds SMPS, JPEG codec, and DFSDM-critical for battery-powered vision/audio edge nodes. Versus i.MX RT1176DVMAA, it trades peak CPU speed for integrated power management and analog subsystems, reducing system-level complexity in industrial IoT deployments.
Availability
STM32H755XIH6 is available at Aetrix Electronics and suitable for industrial PLCs, edge AI gateways, secure IoT endpoints, and high-fidelity audio processors requiring stable component supply across long-lifecycle programs.
Supply support for STM32H755XIH6 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, specializing in microcontrollers, power management, and automotive ICs with strong industrial and IoT focus.
The STM32H7 series targets high-end embedded applications demanding real-time determinism, security, and rich peripheral integration-designed specifically for next-generation industrial automation, medical devices, and intelligent edge systems.
FAQ
What is the maximum operating frequency of each core in the STM32H755XIH6?
The Arm Cortex-M7 core operates up to 480 MHz (1027 DMIPS), while the Cortex-M4 core runs up to 240 MHz (300 DMIPS). Both frequencies are achievable simultaneously under specified voltage and temperature conditions (1.26–1.32 V VCORE, -40°C to 105°C), with dynamic voltage scaling enabled via the SMPS regulator.
Does the STM32H755XIH6 support secure boot and firmware authentication?
Yes-it includes ROM-based secure boot with hash verification, ROP/PC-ROP protection against code reuse attacks, active tamper detection with erase-on-intrusion, and hardware-accelerated AES/HASH/RNG for cryptographic signature validation during firmware update. Secure access mode isolates trusted execution environments.
What are the key differences between the TFBGA240+25 and UFBGA176+25 packages for this MCU?
The TFBGA240+25 (14×14 mm) provides full peripheral access-including all 168 GPIOs, dual CAN FD, Ethernet MAC, and Quad-SPI-while the UFBGA176+25 (10×10 mm) omits certain analog interfaces (e.g., second OPAMP, some ADC channels) and reduces GPIO count to 139. Thermal resistance (θJA) is 22.5°C/W vs. 28.3°C/W respectively.
Can the STM32H755XIH6 operate from a single 3.3 V supply without external regulators?
No-VCORE requires a regulated 1.1 V supply. The integrated SMPS or LDO must be configured: SMPS needs external inductor/capacitor and feedback components; LDO requires 1.7–3.6 V input. I/Os accept 1.62–3.6 V, but analog supplies (VDDA) and SMPS feedback pins demand strict external decoupling per DS12919 Section 6.3.2.
STM32H755XIH6 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Package/Case:
- 265-TFBGA
- Series:
- STM32H7
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- ARM® Cortex®-M4/M7
- Core Size:
- 32-Bit Dual-Core
- Speed:
- 240MHz, 480MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, IrDA, LINbus, MDIO, MMC/SD/SDIO, QSPI, SAI, SPDIF, SPI, SWPMI, UART/USART, USB OTG
- Peripherals:
- Brown-out Detect/Reset, DMA, I2S, LCD, POR, PWM, WDT
- Number of I/O:
- 168
- Program Memory Size:
- 2MB (2M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 1M x 8
- Voltage - Supply (Vcc/Vdd):
- 1.62V ~ 3.6V
- Data Converters:
- A/D 36x16b; D/A 2x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
STM32H755XIH6 FAQ
1.How can I place an order for STM32H755XIH6 through Aetrix?
Please submit a Request for Quotation (RFQ) for STM32H755XIH6 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for STM32H755XIH6 reliable?
The price and inventory of STM32H755XIH6 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for STM32H755XIH6 is usually 5 days.
3.What payment methods are accepted for STM32H755XIH6?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for STM32H755XIH6 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for STM32H755XIH6?
STM32H755XIH6 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your STM32H755XIH6 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for STM32H755XIH6?
For technical support, including STM32H755XIH6 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your STM32H755XIH6 requirements.
6.How does Aetrix verify that STM32H755XIH6 is sourced from the original manufacturer or authorized distributors?
All STM32H755XIH6 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that STM32H755XIH6 meets industry standards.
7.What is the process for return or replacement of STM32H755XIH6?
All STM32H755XIH6 units undergo pre-shipment inspection (PSI). If there is an issue with STM32H755XIH6, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The STM32H755XIH6 part is unused and in its original packaging.
Return procedure for STM32H755XIH6:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
STM32H755XIH6 Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

