STMicroelectronics STM32H755ZIT6
- Part No.:
- STM32H755ZIT6
- Manufacturer:
- STMicroelectronics
- Category:
- Microcontrollers
- Package:
- 144-LQFP
- Datasheet:
-
STM32H755ZIT6.pdf
- Description:
- IC MCU 32BIT 2MB FLASH 144LQFP
- Quantity:
- Payment:

- Shipping:

Inventory:283
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
STM32H755ZIT6 from STMicroelectronics is a dual-core 32-bit Arm® Cortex®-M7 (480 MHz) + Cortex®-M4 (240 MHz) microcontroller with 2 MB flash, 1 MB RAM (192 KB TCM), integrated SMPS regulator, hardware JPEG codec, and cryptographic acceleration (AES-256, SHA-2, RNG). It serves as a high-performance application processor in industrial HMI, motor control gateways, and edge AI inference nodes requiring deterministic real-time response and rich peripheral integration.
For engineers reviewing the STM32H755ZIT6 datasheet, STM32H755ZIT6 pinout, STM32H755ZIT6 application, or STM32H755ZIT6 equivalent, key selection considerations include dual-core asymmetric execution capability, 168 GPIOs with interrupt support, TFBGA240+25 package pin mapping, and domain-specific power management across D1/D2/D3 domains.
Technical Context
The device implements a triple-domain power architecture (D1 for M7 core & graphics, D2 for comms peripherals, D3 for reset/clock/power control), enabling independent clock gating and voltage scaling across six configurable ranges. Its interconnect matrix comprises one AXI and two AHB bus matrices with five AHB2-APB and two AXI2-AHB bridges to manage concurrent high-bandwidth traffic from up to 35 communication interfaces.
Dual-core operation is coordinated via shared memory with hardware semaphore support and cache coherency maintained through L1 instruction/data caches (16 KB each on M7) and ART Accelerator for flash access. The MDMA controller supports linked-list DMA transfers, while dual-port DMAs offload CPU-intensive data movement for ADC, camera, and audio streams.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Cores | Dual: Cortex-M7 @ 480 MHz (1027 DMIPS) + Cortex-M4 @ 240 MHz (300 DMIPS); enables asymmetric task partitioning (e.g., M7 for vision/AI, M4 for real-time control) |
| Memory | 2 MB flash (read-while-write), 1 MB RAM (192 KB TCM + 864 KB SRAM + 4 KB backup SRAM); supports time-critical code in ITCM and large buffers in user SRAM |
| Power Management | SMPS step-down converter + LDO; 6 voltage scaling ranges in Run/Stop modes; 2.95 µA Standby current (RTC/LSE ON, Backup SRAM OFF) |
| Analog Peripherals | 3× 16-bit ADCs (3.6 MSPS), 2× 12-bit DACs (1 MHz), 2× op-amps (7.3 MHz GBW), DFSDM with 8 channels; suitable for precision sensor fusion and closed-loop analog control |
| Communication | 2× CAN FD, 2× USB OTG (FS/HS), Ethernet MAC, HDMI-CEC, SPDIFRX, 4× I2C, 4× USART/UART, 6× SPI, SDMMC ×2; meets industrial gateway and multimedia endpoint requirements |
| Graphics & Media | LCD-TFT controller (XGA), Chrom-ART DMA2D accelerator, hardware JPEG codec; enables local GUI rendering without external GPU or frame buffer overhead |
| Cryptography | AES-128/192/256, HASH (SHA-1/SHA-2), HMAC, TRNG; provides secure boot, firmware update signing, and encrypted data channel establishment |
Pinout & Package
STM32H755ZIT6 uses a TFBGA240+25 (14 × 14 mm) package with 240 balls plus 25 dedicated VSS/VDD pairs, supporting fine-pitch PCB layout and thermal dissipation for sustained 480 MHz operation. Pin functions are validated per ST's DS12919 Rev 3, Section 5 (Pinout, pin description and alternate functions).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD, VDDA, VDDIO2 | Supply rails | VDD (1.62–3.6 V digital core), VDDA (analog domain), VDDIO2 (I/O bank 2); decoupling required per Section 6.3.2 of datasheet |
| VCAP_1, VCAP_2 | Core regulator bypass | Connect 2.2 µF ceramic capacitors to stabilize internal SMPS output feeding VCORE; mandatory for reliable 480 MHz operation |
| NRST | Active-low reset | Asynchronous reset input with Schmitt trigger; drives system-wide reset including both cores and peripherals upon assertion |
| BOOT0 | Boot mode select | High at power-up selects system memory bootloader; used for field firmware recovery without debugger |
| PA0–PA15, PB0–PB15, etc. | GPIO banks | 168 total I/Os with interrupt capability; multiple alternate functions per pin (e.g., TIMx_CHy, USARTx_TX, FMC_Ax) mapped in Table 8 of datasheet |
Key Features
| Feature | Design Value |
|---|---|
| Dual-core asymmetric processing | Enables concurrent execution of latency-sensitive control (M4) and compute-intensive tasks (M7), reducing need for external co-processors |
| Integrated SMPS regulator | Replaces external DC-DC converter, lowering BOM count and improving efficiency over LDO-only solutions in battery-powered or thermally constrained designs |
| Hardware JPEG codec | Offloads CPU from image compression/decompression; achieves real-time encoding of VGA frames at <10 ms latency |
| DFSDM with 8 channels | Supports simultaneous sigma-delta sensor inputs (e.g., current/voltage sensing in motor drives) with digital filtering and decimation in hardware |
| Chrom-ART DMA2D accelerator | Performs 2D graphics operations (copy, blend, format conversion) without CPU involvement, cutting GUI rendering time by >70% vs software-only |
Applications
| Industrial Motor Control Gateway | Edge AI Vision Node |
|---|---|
Use Scenario: Centralized control unit managing multiple servo drives, collecting sensor data, and running predictive maintenance algorithms. IC Role / Device Role / Timing Role: Dual-core orchestrator: M4 handles real-time PWM generation and encoder feedback (sub-µs jitter), M7 runs EtherCAT stack and ML inference on vibration spectra. Use Value: Eliminates need for separate FPGA or DSP; SMPS enables compact heatsink-free enclosure; 2× CAN FD supports legacy drive communication. | Use Scenario: Localized object detection camera in smart factory, operating standalone with onboard inference and low-latency alert triggering. IC Role / Device Role / Timing Role: Vision processor: DCMI captures 80 MHz parallel sensor data, JPEG codec compresses frames, M7 executes quantized CNN model, M4 manages USB/SD card storage. Use Value: Hardware JPEG reduces bandwidth to host by 8×; TCM RAM ensures deterministic inference timing; 16-bit ADCs monitor ambient light/temperature for auto-exposure calibration. |
| Human-Machine Interface (HMI) | Secure Industrial Gateway |
Use Scenario: Touch-enabled panel PC for machine monitoring, displaying real-time process data and accepting operator commands. IC Role / Device Role / Timing Role: Application processor: LTDC drives XGA display, Chrom-ART renders UI elements, touch controller interface runs on dedicated LPUART, crypto engine secures OTA updates. Use Value: On-chip graphics accelerator eliminates external frame buffer RAM; 192 KB TCM holds critical UI rendering routines for consistent 60 fps refresh. | Use Scenario: Protocol translator bridging Modbus RTU field devices to cloud via TLS-secured MQTT over Ethernet or cellular. IC Role / Device Role / Timing Role: Secure communications hub: Ethernet MAC handles TCP/IP stack, crypto accelerators perform AES-GCM encryption and SHA-256 certificate validation, RTC enables time-stamped audit logs. Use Value: Hardware TRNG and ROP/PC-ROP prevent firmware cloning; SMPS improves power efficiency during long idle periods between polling cycles. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-core Arm Cortex-M7/M4 microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| STM32H745ZIT6 | No hardware JPEG codec; 1 MB flash, same 1 MB RAM; identical pinout and package | Lacks on-chip image compression - requires external memory or CPU-based encoding for vision use cases | Select when JPEG acceleration is unnecessary and cost reduction is prioritized over media processing capability |
| NXP i.MX RT1176DVMAA | Single Cortex-M7 @ 1 GHz + Cortex-M4 @ 400 MHz; 2 MB SRAM, no embedded flash; BGA289 package | Requires external QSPI flash; higher M7 clock but lacks integrated SMPS and analog peripherals (no DAC/op-amp/DFSDM) | Choose for ultra-high compute throughput where external memory and discrete power design are acceptable trade-offs |
Compared with STM32H745ZIT6, the STM32H755ZIT6 adds JPEG codec and 1 MB extra flash for firmware flexibility; versus i.MX RT1176DVMAA, it integrates SMPS, analog front-end, and flash-reducing external components and simplifying certification for industrial safety standards.
Availability
STM32H755ZIT6 is available at Aetrix Electronics and suitable for industrial motor control gateways, edge AI vision nodes, human-machine interfaces, and secure industrial gateways requiring stable component supply across multi-year production cycles.
Supply support for STM32H755ZIT6 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power management ICs, sensors, and automotive semiconductors since 1987.
The STM32H7 series targets high-end embedded applications demanding real-time determinism, rich connectivity, and advanced security - specifically engineered for industrial automation, medical imaging, and intelligent edge devices.
FAQ
What is the maximum operating frequency of each core in the STM32H755ZIT6?
The Cortex-M7 core operates at up to 480 MHz with double-precision FPU and 16 KB instruction/data caches, delivering 1027 DMIPS. The Cortex-M4 core runs at up to 240 MHz with single-precision FPU and ART Accelerator support, achieving 300 DMIPS. Both frequencies are validated under full voltage scaling range 0 (1.26 V) per DS12919 Rev 3, Section 6.3.4.
Does the STM32H755ZIT6 support external SDRAM, and what interface is used?
Yes, it supports external SDRAM up to 125 MHz using the Flexible Memory Controller (FMC) with a 32-bit data bus. The FMC also handles PSRAM, NOR/NAND flash, and SRAM. Configuration requires precise timing parameters from Section 6.3.18 of DS12919 Rev 3 and proper PCB layout for signal integrity.
How does the SMPS regulator integrate with the core voltage supply?
The integrated SMPS step-down converter directly supplies VCORE and can optionally power external circuitry. It requires two external components: a 2.2 µH inductor and a 22 µF output capacitor. VCAP_1/VCAP_2 pins must be decoupled with 2.2 µF ceramics to stabilize regulation, as specified in Section 6.3.3 of the datasheet.
Can the STM32H755ZIT6 execute code from external Quad-SPI flash memory?
Yes, it supports XIP (execute-in-place) from Quad-SPI flash via the QUADSPI interface running up to 133 MHz. The ART Accelerator caches instruction fetches to eliminate wait states, enabling near-zero latency execution. This configuration is validated in AN5190 and requires proper memory-mapped address setup in the system linker script.
STM32H755ZIT6 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Package/Case:
- 144-LQFP
- Series:
- STM32H7
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- ARM® Cortex®-M4/M7
- Core Size:
- 32-Bit Dual-Core
- Speed:
- 240MHz, 480MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, IrDA, LINbus, MDIO, MMC/SD/SDIO, QSPI, SAI, SPDIF, SPI, SWPMI, UART/USART, USB OTG
- Peripherals:
- Brown-out Detect/Reset, DMA, I2S, LCD, POR, PWM, WDT
- Number of I/O:
- 97
- Program Memory Size:
- 2MB (2M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 1M x 8
- Voltage - Supply (Vcc/Vdd):
- 1.62V ~ 3.6V
- Data Converters:
- A/D 23x16b; D/A 2x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
STM32H755ZIT6 FAQ
1.How can I place an order for STM32H755ZIT6 through Aetrix?
Please submit a Request for Quotation (RFQ) for STM32H755ZIT6 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for STM32H755ZIT6 reliable?
The price and inventory of STM32H755ZIT6 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for STM32H755ZIT6 is usually 5 days.
3.What payment methods are accepted for STM32H755ZIT6?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for STM32H755ZIT6 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for STM32H755ZIT6?
STM32H755ZIT6 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your STM32H755ZIT6 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for STM32H755ZIT6?
For technical support, including STM32H755ZIT6 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your STM32H755ZIT6 requirements.
6.How does Aetrix verify that STM32H755ZIT6 is sourced from the original manufacturer or authorized distributors?
All STM32H755ZIT6 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that STM32H755ZIT6 meets industry standards.
7.What is the process for return or replacement of STM32H755ZIT6?
All STM32H755ZIT6 units undergo pre-shipment inspection (PSI). If there is an issue with STM32H755ZIT6, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The STM32H755ZIT6 part is unused and in its original packaging.
Return procedure for STM32H755ZIT6:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
STM32H755ZIT6 Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

