STMicroelectronics STM32H7S3I8K6
- Part No.:
- STM32H7S3I8K6
- Manufacturer:
- STMicroelectronics
- Category:
- Microcontrollers
- Package:
- 201-UFBGA
- Datasheet:
-
STM32H7S3I8K6.pdf
- Description:
- IC MCU 32BIT 64KB FLASH 176UFBGA
- Quantity:
- Payment:

- Shipping:

Inventory:2,156
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
STM32H7S3I8K6 from STMicroelectronics is an Arm® Cortex®-M7 32-bit microcontroller operating at up to 600 MHz, featuring 64 KB flash, 620 KB SRAM (548 KB with ECC), dual FD-CAN interfaces, Ethernet MAC, and hardware-accelerated graphics (NeoChrom GPU2D + Chrom-ART DMA2D). It targets high-performance industrial HMI, secure edge gateways, and real-time vision-enabled control systems.
For engineers reviewing the STM32H7S3I8K6 datasheet, STM32H7S3I8K6 pinout, STM32H7S3I8K6 application, or STM32H7S3I8K6 equivalent, key selection criteria include FD-CAN timing compliance, TCM RAM allocation for deterministic code execution, on-the-fly external memory encryption capability, and PSA Level 2/SESIP Level 3 security certification status.
Technical Context
This MCU integrates a dual-bank Arm Cortex-M7 core with tightly coupled memory (64+64 KB TCM), L1 instruction/data caches (32+32 KB), and dual-port DMA controllers optimized for concurrent peripheral-to-memory transfers. Its clock system includes PLLs supporting precise USB/Ethernet timing and a dedicated 48 MHz HSI48 oscillator for USB OTG operation.
The device implements a hierarchical memory architecture: AXI SRAM (384 KB), backup SRAM (4 KB), and flexible external memory controller supporting SDR/LPSDR SDRAM, NOR/NAND, and octo-SPI HyperRAM™ at up to 200 MHz. Security is enforced via Root of Trust, Secure Hide Protection Area (HDP), and two DPA-resistant AES coprocessors.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | Arm Cortex-M7 @ 600 MHz with DP-FPU, MPU, and 32+32 KB L1 cache enabling zero-wait-state execution from flash or external memory. |
| Memory | 64 KB user flash; 620 KB SRAM (548 KB with ECC) split into 64+64 KB TCM, 384 KB AXI, and 4 KB backup SRAM for RTC retention. |
| Security | PSA Level 2 and SESIP Level 3 certified; hardware root of trust, secure boot, embedded RSS for SFU, and DPA-resistant AES/PKA accelerators. |
| Graphics | NeoChrom GPU2D for rotation/scaling, Chrom-ART DMA2D for 2D composition, Chrom-GRC GFXMMU for 20% resource optimization, and hardware JPEG codec. |
| Connectivity | 2× FD-CAN, Ethernet MAC with DMA, 2× USB OTG (FS + HS), 1× USB Type-C PD controller, 3× I2C, 1× I3C, 9× SPI/I2S, 2× SAI, SPDIF-IN, HDMI-CEC. |
| Analog & Timing | 2× 12-bit ADC @ 5 MSPS (17 channels), CORDIC for trigonometric acceleration, RTC with sub-second calendar, and 23 timers including 5 low-power 16-bit timers active in Stop mode. |
Pinout & Package
STM32H7S3I8K6 is packaged in VFQFPN68 (10 × 10 mm, 0.5 mm pitch), a thermally enhanced quad flat no-lead package suitable for space-constrained industrial and automotive applications requiring robust thermal performance and EMI resilience.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD, VDDA, VDDIO2 | Core, analog, and I/O power supplies | Supports 1.71–3.6 V operation; VDDA powers ADC/DAC/temperature sensors; VDDIO2 enables independent I/O voltage scaling. |
| VCAP1, VCAP2 | Core voltage decoupling | Requires external 2.2 µF ceramic capacitors per pin to stabilize internal SMPS-regulated VCORE (1.1 V typical). |
| NRST | Active-low reset input | Asynchronous reset signal with internal pull-up; compatible with open-drain or push-pull reset sources per IEC 61000-4-2 Level 4. |
| BOOT0 | Boot mode selection | High at power-up selects system memory bootloader; low selects user flash; sampled only during reset assertion. |
| PA13/PA14 | SWD debug interface | Serial Wire Debug (SWD) clock and data pins; support authenticated debug access with certificate-based lifecycle management. |
| PD0/PD1 | Ethernet PHY interface | RMII clock and data lines for 10/100 Mbps Ethernet MAC; require 50 Ω impedance-controlled routing and 3.3 V tolerant I/O. |
Key Features
| Feature | Design Value |
|---|---|
| Secure Boot & Firmware Update | Hardware-enforced root of trust with unique boot entry, HDP-protected secure hide area, and embedded RSS enabling signed, encrypted SFU without external secure element. |
| On-the-Fly Memory Encryption | MCE engine encrypts/decrypts serial (octo-SPI) and parallel (FMC) external memories in real time using AES-128/256, preventing firmware extraction from off-chip storage. |
| Dual FD-CAN with Time-Triggered Communication | Two ISO 11898-1:2015-compliant FD-CAN controllers supporting bit rates up to 5 Mbps, loopback self-test, and time-triggered transmission for deterministic automotive networking. |
| Graphics Acceleration Stack | NeoChrom GPU2D handles affine transforms and texture mapping; Chrom-ART DMA2D performs alpha blending and image copy; Chrom-GRC optimizes framebuffer memory bandwidth by 20%. |
| Low-Power Determinism | Five low-power 16-bit timers retain counting in Stop mode; 4 KB backup SRAM retains context across deep sleep; VBAT-powered RTC maintains calendar accuracy ±1 ppm over temperature. |
Applications
| Industrial HMI Panel | Secure Edge Gateway |
|---|---|
Use Scenario: Touch-enabled factory floor display with real-time PLC data visualization and local alarm logging. IC Role / Device Role / Timing Role: Primary application processor executing FreeRTOS with GUI framework, managing LCD-TFT controller (XGA), touch controller I2C, and Ethernet MAC for OPC UA communication. Use Value: NeoChrom GPU2D renders rotating gauges and animated transitions at 60 fps without CPU load; Chrom-GRC reduces framebuffer memory bandwidth by 20%, lowering FMC power consumption. |
Use Scenario: Field-deployable IoT gateway aggregating Modbus RTU sensor data, performing TLS-secured MQTT uploads, and hosting local web UI. IC Role / Device Role / Timing Role: Dual-core-capable host MCU running Linux Lite or bare-metal TLS stack, interfacing with RS485 transceivers, SD card, and Wi-Fi module via USB OTG HS. Use Value: PSA Level 2-certified secure boot prevents unauthorized firmware loading; on-the-fly AES encryption protects sensor logs stored on external eMMC; FD-CAN monitors local fieldbus diagnostics. |
| Real-Time Vision Controller | Automotive Diagnostic Tool |
Use Scenario: Compact machine vision node capturing VGA images via parallel camera interface, applying edge detection, and triggering pneumatic actuators. IC Role / Device Role / Timing Role: Image acquisition and preprocessing unit using DCMIPP for pixel cropping/format conversion, CORDIC for angle calculation, and GPIO-timed PWM outputs. Use Value: DCMIPP processes raw Bayer data at 30 fps with hardware cropping; 5 MSPS ADC samples analog feedback signals synchronously with image capture; TCM RAM ensures deterministic interrupt latency <1 µs. |
Use Scenario: Handheld OBD-II scanner supporting UDS diagnostics over CAN FD, displaying live PID streams, and updating firmware via USB-C PD. IC Role / Device Role / Timing Role: Diagnostic protocol handler with dual FD-CAN controllers-one for vehicle bus monitoring, one for UCPD negotiation-and USB Type-C PD controller managing power delivery negotiation. Use Value: FD-CAN supports ISO 11898-1:2015 bit rates up to 5 Mbps for fast diagnostic session handshaking; UCPD manages VCONN and SOP' signaling compliant with USB PD 3.0 specification. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar high-performance secure MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| STM32H753VI | Higher flash (2 MB vs. 64 KB), no FD-CAN, lacks NeoChrom GPU2D and Chrom-GRC, but adds Octo-SPI with XiP and larger TCM (192 KB). | Better suited for complex embedded Linux applications requiring large code footprint and XiP execution, not FD-CAN–based automotive diagnostics. | Select when external flash boot and deterministic XiP execution outweigh FD-CAN and graphics acceleration needs. |
| RA8T1A002FGB | Renesas RA8 core @ 480 MHz, 2 MB flash, 1 MB SRAM, no FD-CAN, includes TrustZone-A but no PSA/SESIP certification, single USB HS port. | Targets industrial motor control with integrated FPU and timer peripherals optimized for three-phase PWM, not multimedia or secure gateway use cases. | Choose for cost-sensitive servo drives where TrustZone-A suffices and FD-CAN/Ethernet are unnecessary. |
Compared with STM32H753VI and RA8T1A002FGB, the STM32H7S3I8K6 uniquely balances FD-CAN timing precision, PSA-certified security, and hardware-accelerated graphics-making it optimal for compact, secure, real-time HMI and edge gateway designs where external memory encryption and deterministic rendering are mandatory.
Availability
STM32H7S3I8K6 is available at Aetrix Electronics and suitable for industrial HMI panels, secure edge gateways, real-time vision controllers, and automotive diagnostic tools requiring stable component supply across multi-year production cycles.
Supply support for STM32H7S3I8K6 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, specializing in microcontrollers, power management, sensors, and automotive ICs with vertical manufacturing and broad IP licensing.
The STM32H7S series is designed for secure, graphics-rich, real-time edge devices-emphasizing PSA/SESIP-certified security, FD-CAN timing determinism, and hardware-accelerated 2D graphics for industrial and automotive human-machine interfaces.
FAQ
What is the maximum operating frequency and associated CoreMark score?
The STM32H7S3I8K6 operates at up to 600 MHz with a measured CoreMark score of 3196 (5.33 CoreMark/MHz), validated under full cache and TCM enablement per ARM CoreMark benchmark v1.0. This reflects deterministic execution with zero-wait-state flash access enabled by 32+32 KB L1 instruction/data caches.
Does this MCU support hardware-accelerated JPEG encoding or decoding?
Yes, the STM32H7S3I8K6 includes a dedicated hardware JPEG codec supporting both encoding and decoding of baseline JPEG streams up to QVGA resolution at real-time frame rates. The codec operates independently of the CPU and interfaces directly with DMA2D and memory controllers for zero-copy processing.
How is security certification verified for production units?
Each STM32H7S3I8K6 wafer lot undergoes PSA Level 2 and SESIP Level 3 conformance testing per GlobalPlatform standards, with certification documentation (GP-TEE-001, SESIP-003) published on ST's official product page. Certification applies to silicon, ROM bootloader, and embedded secure services-not customer firmware.
What external memory interfaces support execute-in-place (XiP) operation?
The STM32H7S3I8K6 supports XiP exclusively through its octo-SPI interface (XSPI), which can run at up to 200 MHz with HyperRAM™/HyperFlash™ frame formats. The hexa-SPI variant does not support XiP; parallel FMC interfaces require code relocation to internal SRAM or TCM for execution.
STM32H7S3I8K6 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Package/Case:
- 201-UFBGA
- Series:
- STM32H7
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- ARM® Cortex®-M7
- Core Size:
- 32-Bit
- Speed:
- 600MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, IrDA, LINbus, MDIO, MMC/SD/SDIO, QSPI, SAI, SPDIF, SPI, SWPMI, UART/USART, USB OTG
- Peripherals:
- Brown-out Detect/Reset, DMA, I2S, POR, PWM, WDT
- Number of I/O:
- 122
- Program Memory Size:
- 64KB (64K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 616K x 8
- Voltage - Supply (Vcc/Vdd):
- 1.71V ~ 3.6V
- Data Converters:
- A/D 18x12b
- Oscillator Type:
- External, Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
STM32H7S3I8K6 FAQ
1.How can I place an order for STM32H7S3I8K6 through Aetrix?
Please submit a Request for Quotation (RFQ) for STM32H7S3I8K6 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for STM32H7S3I8K6 reliable?
The price and inventory of STM32H7S3I8K6 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for STM32H7S3I8K6 is usually 5 days.
3.What payment methods are accepted for STM32H7S3I8K6?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for STM32H7S3I8K6 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for STM32H7S3I8K6?
STM32H7S3I8K6 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your STM32H7S3I8K6 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for STM32H7S3I8K6?
For technical support, including STM32H7S3I8K6 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your STM32H7S3I8K6 requirements.
6.How does Aetrix verify that STM32H7S3I8K6 is sourced from the original manufacturer or authorized distributors?
All STM32H7S3I8K6 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that STM32H7S3I8K6 meets industry standards.
7.What is the process for return or replacement of STM32H7S3I8K6?
All STM32H7S3I8K6 units undergo pre-shipment inspection (PSI). If there is an issue with STM32H7S3I8K6, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The STM32H7S3I8K6 part is unused and in its original packaging.
Return procedure for STM32H7S3I8K6:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
STM32H7S3I8K6 Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

