STMicroelectronics STM32L552CET6P
- Part No.:
- STM32L552CET6P
- Manufacturer:
- STMicroelectronics
- Category:
- Microcontrollers
- Package:
- 48-LQFP
- Datasheet:
-
STM32L552CET6P.pdf
- Description:
- IC MCU 32BIT 512KB FLASH 48LQFP
- Quantity:
- Payment:

- Shipping:

Inventory:3,496
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
STM32L552CET6P from STMicroelectronics is an ultra-low-power Arm® Cortex®-M33 32-bit microcontroller with TrustZone® security, FPU, and SMPS support. It delivers 165 DMIPS at up to 110 MHz, integrates 512 KB Flash (dual-bank read-while-write), 256 KB SRAM (64 KB with hardware parity), and operates from 1.71–3.6 V across –40 °C to 125 °C. Used in secure, battery-powered edge nodes requiring real-time processing, cryptographic services, and sub-μA standby operation.
For engineers reviewing the STM32L552CET6P datasheet, STM32L552CET6P pinout, STM32L552CET6P application, or STM32L552CET6P equivalent, key selection criteria include TrustZone-enforced memory isolation, SMPS efficiency (62 μA/MHz @ 3 V), ULPMark-CP® score of 370, and dual 12-bit ADCs with 5 Msps sampling - critical for secure sensor fusion and low-energy industrial IoT endpoints.
Technical Context
The STM32L552CET6P implements a dual-bank Flash architecture enabling seamless firmware updates without halting execution, paired with an 8-KB ART Accelerator instruction cache for zero-wait-state operation at 110 MHz. Its TrustZone® subsystem enforces hardware-isolated secure/non-secure worlds via SAU and GTZC, supporting secure boot from immutable ROM and runtime attestation.
Power management combines an integrated SMPS step-down converter (62 μA/MHz), LDO regulator with three output ranges, and seven low-power modes - including 17 nA Shutdown and 222 nA Standby with RTC - all coordinated by a dedicated PWR TrustZone controller to prevent privilege escalation during state transitions.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | Arm Cortex-M33 with TrustZone®, FPU, MPU, 165 DMIPS @ 110 MHz - enables secure real-time control and DSP workloads in single-chip edge AI inference. |
| Memory | 512 KB Flash (2 banks, RWW), 256 KB SRAM (64 KB parity-protected) - supports atomic OTA updates and ECC-protected data buffers for safety-critical logging. |
| Low-Power Performance | 17 nA Shutdown mode (5 wakeup pins), 3.16 μA Stop 2 with RTC - extends coin-cell battery life beyond 10 years in metering and asset trackers. |
| Analog Peripherals | 2× 12-bit ADCs (5 Msps, 16-bit oversampling), 2× DACs, 2× op-amps with PGA, 2× comparators - enables high-fidelity sensor signal conditioning without external components. |
| Security Features | TrustZone® isolation, 96-bit unique ID, NIST SP800-90B TRNG, HASH accelerator, SFI with embedded RSS, active tamper detection - meets PSA Level 3 and SESIP certification prerequisites. |
| Communication | 1× FDCAN, 6× USART (LIN/IRDA/ISO7816), 4× I²C FM+, 2× SAI, USB FS + UCPD - supports automotive diagnostics, audio streaming, and USB-C PD negotiation in compact form factors. |
| Package & Pin Count | LQFP48 (7 × 7 mm), 48-pin, 36 general-purpose I/Os (5 V-tolerant, 14 with independent supply down to 1.08 V) - fits space-constrained designs with mixed-voltage peripheral interfacing. |
Pinout & Package
LQFP48 package (7 × 7 mm, 0.5 mm pitch), thermally enhanced with exposed thermal pad. Compatible with standard reflow profiles and IPC Class 2/3 assembly.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD, VDDA, VDDIO2 | Power supply inputs | Dedicated domains: VDD (digital core), VDDA (analog), VDDIO2 (I/O bank 2) - enable independent voltage scaling and noise isolation for mixed-signal integrity. |
| VSS, VSSA, VSSIO2 | Ground returns | Separate analog/digital/power-ground planes reduce coupling noise and improve ADC/DAC SNR performance. |
| PA0–PA15, PB0–PB15, PC0–PC15, PD0–PD15, PF0–PF1 | General-purpose I/Os | 36 total GPIOs; up to 14 support independent 1.08–3.6 V supply - allows direct interface to low-voltage sensors and legacy 5 V peripherals. |
| NRST | Active-low reset input | Asynchronous reset with internal pull-up; compatible with external RC or supervisor ICs for robust power-on sequencing. |
| BOOT0 | Boot mode selection | Configures boot source (system memory, Flash, or SRAM); requires external pull-up/down for factory programming or recovery mode entry. |
| OSC_IN / OSC_OUT | External crystal oscillator terminals | Supports 4–48 MHz crystals; enables precise clocking for USB, RTC, and communication timing-critical functions. |
| VBAT | RTC and backup register supply | Accepts 1.65–3.6 V; sustains RTC calendar and 32×32-bit registers in 187 nA VBAT mode during main power loss. |
Key Features
| Feature | Design Value |
|---|---|
| FlexPowerControl architecture | Seven configurable low-power modes with sub-200 nA shutdown - eliminates need for external power supervisors in battery-backed applications. |
| ART Accelerator + 8 KB I-Cache | Zero-wait-state execution from Flash at 110 MHz - reduces code size overhead and improves deterministic interrupt latency vs. uncached M33 cores. |
| SMPS + LDO dual-regulator system | 62 μA/MHz efficiency @ 3 V (SMPS) vs. 106 μA/MHz (LDO) - cuts active-mode power by 42% in always-on sensor hubs and wearable health monitors. |
| TrustZone® + GTZC + SAU | Hardware-enforced secure/non-secure memory and peripheral partitioning - enables certified secure bootloader, encrypted firmware update, and isolated crypto key storage. |
| OCTOSPI interface | Supports x8/octal SPI NOR/FRAM with execute-in-place (XIP) - replaces parallel memories in space-constrained designs while maintaining >80 MB/s throughput. |
Applications
| Smart Utility Metering | Secure Wearable Health Monitor |
|---|---|
Use Scenario: Battery-powered electricity/water/gas meters with remote firmware updates and tamper detection. IC Role / Device Role / Timing Role: Main MCU executing metrology algorithms, managing secure OTA updates via FDCAN/USB, and maintaining RTC calendar during mains outage. Use Value: 187 nA VBAT mode sustains 10+ year battery life; TrustZone® isolates metering firmware from update stack; 222 nA Standby with RTC enables accurate billing intervals. | Use Scenario: Clinical-grade ECG/PPG patch with Bluetooth LE connectivity and on-device arrhythmia detection. IC Role / Device Role / Timing Role: Sensor hub aggregating analog biosignals, running ML inference on secure SRAM, and encrypting data before BLE transmission. Use Value: Dual 12-bit ADCs sample ECG at 5 Msps with hardware oversampling; 64 KB parity-protected SRAM ensures data integrity; TRNG feeds TLS 1.3 handshakes. |
| Industrial Wireless Sensor Node | USB-C Power Delivery Endpoint |
Use Scenario: LoRaWAN/NB-IoT node monitoring temperature, vibration, and humidity in harsh factory environments. IC Role / Device Role / Timing Role: Edge processor performing FFT-based anomaly detection, managing low-power radio sleep cycles, and securing sensor data with AES-256. Use Value: 17 nA Shutdown mode extends shelf life; SMPS efficiency enables solar harvesting; FDCAN interfaces to legacy PLCs without level shifters. | Use Scenario: Smart dock or monitor with USB-C port supporting power delivery negotiation, display alt-mode, and device authentication. IC Role / Device Role / Timing Role: UCPD controller managing PD contract, CC line monitoring, VCONN switching, and Type-C cable orientation detection. Use Value: Integrated UCPD peripheral eliminates external PD controller IC; 5 µs wakeup from Stop mode ensures responsive PD contract renegotiation. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar ultra-low-power secure MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| STM32U575ZIT6 | Higher performance (220 MHz Cortex-M33), larger Flash (2 MB), no SMPS, higher active current (72 μA/MHz) | Better suited for complex GUI or RTOS-heavy applications; lacks integrated SMPS for ultra-low-power battery use cases | Select when compute density outweighs sub-μA standby requirements and external SMPS is acceptable. |
| RA4M3AFGB | Arm Cortex-M4F (100 MHz), 1 MB Flash, 384 KB SRAM, no TrustZone®, different peripheral set (no UCPD/FDCAN) | Targets cost-sensitive industrial HMI; lacks hardware security root-of-trust and USB-C PD capability | Choose for non-security-critical motor control or gateway applications where Renesas ecosystem integration is prioritized. |
Compared with STM32U575ZIT6, the STM32L552CET6P trades peak CPU speed for superior energy efficiency and integrated SMPS - making it optimal for multi-year battery operation. Against RA4M3AFGB, it provides mandatory TrustZone® isolation and UCPD, essential for certified secure USB-C endpoints and regulated medical devices.
Availability
STM32L552CET6P is available at Aetrix Electronics and suitable for smart utility metering, secure wearable health monitors, industrial wireless sensor nodes, and USB-C power delivery endpoints requiring stable component supply across extended product lifecycles.
Supply support for STM32L552CET6P includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power management ICs, sensors, and analog products for industrial, automotive, and consumer markets.
The STM32L5 series targets secure, ultra-low-power edge computing - combining Arm TrustZone®, advanced power gating, and hardware accelerators to meet PSA Certified Level 3 and IEC 62443 requirements for IoT endpoint resilience.
FAQ
What is the maximum operating frequency and corresponding power consumption in Run mode?
The STM32L552CET6P achieves 110 MHz maximum CPU frequency using its internal PLL. In Run mode with SMPS enabled, it consumes 62 μA per MHz at 3 V supply - translating to approximately 6.82 mA total at full speed. With LDO only, consumption rises to 106 μA/MHz (11.66 mA). These values are measured with ART Accelerator and I-Cache enabled, per DS12737 Rev 6 Section 5.3.6.
Does the STM32L552CET6P support true hardware-based secure boot and firmware validation?
Yes. It implements a hardware-rooted secure boot chain starting from immutable ROM loader, verifying signed firmware images using public-key cryptography before execution. The Root of Trust leverages Hide Protection Area (HDP), unique boot entry, and Secure Firmware Installation (SFI) via embedded Root Secure Services (RSS), fully compliant with PSA Certified Level 3 requirements.
How many I/O pins support independent voltage supply, and what is the minimum allowable voltage?
The STM32L552CET6P provides 14 I/Os (grouped as VDDIO2 domain) with independent supply capability, supporting voltages from 1.08 V to 3.6 V. This allows direct interfacing with low-voltage sensors (e.g., 1.2 V or 1.8 V logic) without level shifters, while maintaining full 5 V tolerance on most other GPIOs for legacy peripheral compatibility.
What are the key differences between Stop 2 and Standby modes regarding RTC functionality and wakeup sources?
In Stop 2 mode, the RTC runs from LSE (32 kHz crystal) or LSI, consuming 3.16 μA and retaining full SRAM content; wakeup occurs via EXTI lines, RTC alarms, or I²C address match. In Standby mode, RTC remains active with 222 nA consumption but SRAM is powered off; wakeup is limited to five dedicated pins, RTC alarm, or tamper event - offering deeper power savings at the cost of context retention.
STM32L552CET6P Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Package/Case:
- 48-LQFP
- Series:
- STM32L5
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- ARM® Cortex®-M33
- Core Size:
- 32-Bit Single-Core
- Speed:
- 110MHz
- Connectivity:
- CANbus, I2C, IrDA, LINbus, MMC/SD, QSPI, SAI, SPI, UART/USART, USB
- Peripherals:
- Brown-out Detect/Reset, DMA, PWM, WDT
- Number of I/O:
- 36
- Program Memory Size:
- 512KB (512K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 256K x 8
- Voltage - Supply (Vcc/Vdd):
- 1.71V ~ 3.6V
- Data Converters:
- A/D 9x12b; D/A 2x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
STM32L552CET6P FAQ
1.How can I place an order for STM32L552CET6P through Aetrix?
Please submit a Request for Quotation (RFQ) for STM32L552CET6P on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for STM32L552CET6P reliable?
The price and inventory of STM32L552CET6P are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for STM32L552CET6P is usually 5 days.
3.What payment methods are accepted for STM32L552CET6P?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for STM32L552CET6P transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for STM32L552CET6P?
STM32L552CET6P orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your STM32L552CET6P order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for STM32L552CET6P?
For technical support, including STM32L552CET6P datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your STM32L552CET6P requirements.
6.How does Aetrix verify that STM32L552CET6P is sourced from the original manufacturer or authorized distributors?
All STM32L552CET6P products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that STM32L552CET6P meets industry standards.
7.What is the process for return or replacement of STM32L552CET6P?
All STM32L552CET6P units undergo pre-shipment inspection (PSI). If there is an issue with STM32L552CET6P, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The STM32L552CET6P part is unused and in its original packaging.
Return procedure for STM32L552CET6P:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
STM32L552CET6P Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

