STMicroelectronics STM32L552CET6Q
- Part No.:
- STM32L552CET6Q
- Manufacturer:
- STMicroelectronics
- Category:
- Microcontrollers
- Package:
- 48-LQFP
- Datasheet:
-
STM32L552CET6Q.pdf
- Description:
- IC MCU 32BIT 512KB FLASH 48LQFP
- Quantity:
- Payment:

- Shipping:

Inventory:3,430
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
STM32L552CET6Q from STMicroelectronics is an ultra-low-power Arm® Cortex®-M33 32-bit microcontroller with TrustZone® security, FPU, and SMPS support. It delivers 165 DMIPS at up to 110 MHz, integrates 512 KB Flash (dual-bank read-while-write), 256 KB SRAM (64 KB with hardware parity), and operates from 1.71 V to 3.6 V across –40 °C to 125 °C. It targets secure, battery-constrained edge nodes such as industrial wireless sensors and medical wearables.
For engineers reviewing the STM32L552CET6Q datasheet, STM32L552CET6Q pinout, STM32L552CET6Q application, or STM32L552CET6Q equivalent, key selection criteria include TrustZone-enabled secure boot, sub-100 nA standby current with RTC, dual 12-bit ADCs (5 Msps), integrated SMPS step-down converter, and UCPD-based USB Type-C™ power delivery control.
Technical Context
The STM32L552CET6Q implements a dual-core security architecture: the Cortex-M33 core executes in both Secure and Non-secure states, enforced by SAU and GTZC peripherals. Its ART Accelerator includes an 8-KB instruction cache enabling zero-wait-state execution from Flash at 110 MHz.
Power management integrates three regulators: LDO (configurable output), embedded SMPS step-down converter (62 µA/MHz @ 3 V), and external SMPS support. Low-power modes include Shutdown (17 nA), Standby with RTC (222 nA), and Stop 2 with RTC (3.16 µA), all with 5 wakeup pins and 5 µs wake-up latency.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | Arm Cortex-M33 with TrustZone, FPU, MPU - enables secure firmware partitioning and deterministic real-time signal processing. |
| Max Clock Frequency | 110 MHz - supports high-throughput sensor fusion and cryptographic operations without external clocking. |
| Flash Memory | 512 KB, dual-bank, read-while-write - allows seamless over-the-air updates with zero downtime and no code interruption. |
| SRAM | 256 KB total, including 64 KB with hardware parity - ensures data integrity for safety-critical variables and stack protection. |
| Ultra-Low-Power Modes | 17 nA Shutdown, 222 nA Standby with RTC - extends multi-year battery life in maintenance-free IoT endpoints. |
| Analog Peripherals | 2× 12-bit ADC (5 Msps), 2× DAC, 2× OPAMP, 2× comparator - supports local analog signal conditioning and closed-loop control without external components. |
| Security Features | TrustZone, RDP, HDP, SFI, HASH accelerator, NIST SP800-90B TRNG - meets PSA Level 3 and IEC 62443-3-3 requirements for secure device onboarding. |
Pinout & Package
STM32L552CET6Q uses the LQFP48 (7 × 7 mm) package with 48 pins, rated for industrial temperature range (–40 °C to 125 °C) and RoHS-compliant finish.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD, VSS | Main power supply and ground | Supports 1.71–3.6 V operation; decoupling required per datasheet layout guidelines for SMPS/LDO stability. |
| VDDA, VSSA | Analog power and ground | Independent analog domain supply enables noise-isolated ADC/DAC/OPAMP operation at full resolution. |
| PA0–PA15, PB0–PB15, PC0–PC15, PD0–PD2, PH0–PH1 | General-purpose I/Os | Up to 114 fast I/Os; most are 5 V-tolerant, 14 support independent 1.08–3.6 V supply for mixed-voltage interfacing. |
| NRST | Active-low reset input | Asynchronous reset with internal pull-up; compatible with external reset supervisors and push-button debouncing circuits. |
| BOOT0 | Boot mode selection | Configures boot source (system memory, Flash, or SRAM); level sampled at power-on reset and after exit from Standby. |
| UCPD1_CC1 / UCPD1_CC2 | USB Type-C™ configuration channel | Direct interface to USB-C connector for cable orientation detection, role negotiation, and power delivery policy engine. |
| OSC_IN / OSC_OUT | External crystal oscillator inputs | Supports 4–48 MHz crystals; required for precise USB timing and high-accuracy RTC when using LSE (32 kHz). |
Key Features
| Feature | Design Value |
|---|---|
| FlexPowerControl architecture | Enables dynamic voltage/frequency scaling and mode transitions (Run → Stop → Standby) via software API, reducing average system power by >40% vs fixed-mode MCUs. |
| Embedded SMPS step-down converter | Replaces external DC-DC, cuts board area by 30%, and achieves 62 µA/MHz efficiency at 3 V - critical for coin-cell-powered devices. |
| TrustZone + Root of Trust | Hardware-enforced isolation between secure bootloader, crypto keys, and application firmware; prevents unauthorized firmware modification or memory dump. |
| OCTOSPI interface | Single 8-line serial interface supporting XIP from Octal SPI NOR/PSRAM up to 133 MHz - eliminates parallel memory traces and reduces PCB layer count. |
| Low-power timers (LPTIM1–3) | Operate in Stop mode with 1% accuracy using LSE clock - enables precise periodic wake-up for sensor sampling without CPU intervention. |
Applications
| Industrial Wireless Sensor Node | Portable Medical Wearable |
|---|---|
Use Scenario: Battery-powered vibration/temperature node transmitting encrypted telemetry via BLE or LoRaWAN every 5 minutes. IC Role / Device Role / Timing Role: Main controller executing sensor fusion, AES-128 encryption, and low-power scheduling; RTC triggers periodic wake-up; LPTIM manages sensor sampling intervals. Use Value: 17 nA Shutdown and 5 µs wake-up minimize idle loss; dual ADCs acquire synchronized analog channels; TrustZone isolates crypto keys from application firmware. | Use Scenario: ECG patch with real-time waveform analysis, Bluetooth LE streaming, and 7-day battery life. IC Role / Device Role / Timing Role: Signal processor running digital filters on ADC data; DAC drives reference voltage for analog front-end; UCPD manages USB-C charging negotiation. Use Value: 256 KB SRAM stores multi-second waveform buffers; 12-bit ADC oversampling achieves 16-bit effective resolution; SMPS extends runtime by 2.1× vs LDO-only operation. |
| Secure Smart Meter Interface Module | Asset Tracking Beacon |
Use Scenario: Tamper-resistant module connecting utility meter to NB-IoT network, performing secure firmware updates and event logging. IC Role / Device Role / Timing Role: Secure host MCU managing TLS handshake, OTA update validation, and tamper-detection via TAMP peripheral; RTC maintains time-stamped logs. Use Value: Active tamper detection (voltage/frequency/temp) triggers zeroization; 512 KB Flash accommodates dual-image secure bootloader; HASH accelerator speeds up SHA-256 signature verification. | Use Scenario: GPS-enabled logistics tag reporting location every 4 hours using GNSS + cellular assist, powered by Li-SOCl₂ battery. IC Role / Device Role / Timing Role: System orchestrator managing GPS cold start, cellular attach, and deep-sleep cycles; FDCAN interfaces with vehicle CAN bus for status polling. Use Value: 222 nA Standby with RTC sustains 5+ years on single cell; OCTOSPI boots directly from external PSRAM; 114 I/Os support diverse sensor and modem interfaces. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar ultra-low-power secure MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| STM32U575ZIT6 | Higher performance (220 MHz Cortex-M33), larger Flash (2 MB), enhanced security (PKA, AES-256), but higher active current (115 µA/MHz SMPS mode). | Better suited for complex GUI, AI inference, or multi-protocol gateways where compute headroom matters more than minimal standby. | Select when needing >165 DMIPS or advanced crypto accelerators; avoid if <100 nA standby is mandatory. |
| RA4M3GDB00FHI#AA0 | Arm Cortex-M4F (100 MHz), 1 MB Flash, 384 KB SRAM, no TrustZone, lower ultra-low-power capability (250 nA Standby with RTC). | Targets cost-sensitive industrial HMI or motor control where security is handled externally and power budget allows ~2× higher standby draw. | Choose for Renesas ecosystem alignment or when TrustZone is not required; verify ULPMark-CP score (290) is sufficient. |
Compared with STM32L552CET6Q, STM32U575ZIT6 offers higher compute density and stronger crypto acceleration at the cost of increased standby power, while RA4M3GDB00FHI#AA0 provides broader memory and simpler toolchain support but lacks hardware-enforced security isolation and sub-200 nA low-power modes.
Availability
STM32L552CET6Q is available at Aetrix Electronics and suitable for industrial wireless sensors, portable medical wearables, secure smart meter interfaces, and asset tracking beacons requiring stable component supply across extended product lifecycles.
Supply support for STM32L552CET6Q includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power ICs, sensors, and automotive semiconductors since 1987.
The STM32L5 series is engineered for ultra-low-power, secure edge computing - targeting battery-operated IoT endpoints that require certified security, long service life, and robust analog integration without external support components.
FAQ
What is the maximum operating temperature rating for STM32L552CET6Q?
The STM32L552CET6Q is qualified for industrial temperature range: –40 °C to +125 °C ambient. This rating applies to all LQFP48-packaged variants and is verified per JEDEC JESD22-A104 stress testing. Thermal derating is not required up to 125 °C under specified voltage and load conditions.
Does STM32L552CET6Q support USB Type-C™ Power Delivery communication?
Yes - it integrates a dedicated USB Type-C™ and Power Delivery controller (UCPD) compliant with USB PD 3.0 specification. The UCPD peripheral handles CC line monitoring, SOP message exchange, VCONN switching, and policy engine execution without CPU intervention, enabling fully autonomous PD negotiation.
How many independent power domains does STM32L552CET6Q support for analog peripherals?
It supports three independent analog power domains: VDDA (1.71–3.6 V for ADC/DAC/OPAMP), VREF+ (for DAC reference), and VREFINT (internal 1.2 V reference). Each domain has dedicated regulators and filtering paths, allowing simultaneous operation of ADC, DAC, and OPAMP with minimal crosstalk and full 12-bit linearity.
Can STM32L552CET6Q execute code directly from external OCTOSPI memory?
Yes - its OCTOSPI interface supports Execute-in-Place (XIP) mode from Octal SPI NOR flash or PSRAM. With the OCTOSPI controller configured for memory-mapped mode and proper prefetch settings, code fetches occur transparently at up to 133 MHz, eliminating need for RAM copy and reducing boot time by >60% in large firmware deployments.
STM32L552CET6Q Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Package/Case:
- 48-LQFP
- Series:
- STM32L5
- Packaging:
- Tray
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Core Processor:
- ARM® Cortex®-M33
- Core Size:
- 32-Bit Single-Core
- Speed:
- 110MHz
- Connectivity:
- CANbus, I2C, IrDA, LINbus, MMC/SD, QSPI, SAI, SPI, UART/USART, USB
- Peripherals:
- Brown-out Detect/Reset, DMA, PWM, WDT
- Number of I/O:
- 38
- Program Memory Size:
- 512KB (512K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 256K x 8
- Voltage - Supply (Vcc/Vdd):
- 1.71V ~ 3.6V
- Data Converters:
- A/D 9x12b; D/A 2x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
STM32L552CET6Q FAQ
1.How can I place an order for STM32L552CET6Q through Aetrix?
Please submit a Request for Quotation (RFQ) for STM32L552CET6Q on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for STM32L552CET6Q reliable?
The price and inventory of STM32L552CET6Q are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for STM32L552CET6Q is usually 5 days.
3.What payment methods are accepted for STM32L552CET6Q?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for STM32L552CET6Q transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for STM32L552CET6Q?
STM32L552CET6Q orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your STM32L552CET6Q order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for STM32L552CET6Q?
For technical support, including STM32L552CET6Q datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your STM32L552CET6Q requirements.
6.How does Aetrix verify that STM32L552CET6Q is sourced from the original manufacturer or authorized distributors?
All STM32L552CET6Q products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that STM32L552CET6Q meets industry standards.
7.What is the process for return or replacement of STM32L552CET6Q?
All STM32L552CET6Q units undergo pre-shipment inspection (PSI). If there is an issue with STM32L552CET6Q, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The STM32L552CET6Q part is unused and in its original packaging.
Return procedure for STM32L552CET6Q:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
STM32L552CET6Q Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

