STMicroelectronics STM32L552VET6

Overview

STM32L552VET6 from STMicroelectronics is an ultra-low-power Arm® Cortex®-M33 32-bit microcontroller with TrustZone® security, FPU, and SMPS support. It delivers 165 DMIPS at up to 110 MHz, integrates 512 KB dual-bank Flash and 256 KB SRAM (64 KB with hardware parity), and operates from 1.71 V to 3.6 V across –40 °C to 125 °C. It targets secure, battery-constrained applications such as industrial wireless sensors and medical wearables requiring certified firmware integrity and sub-μA standby operation.

For engineers reviewing the STM32L552VET6 datasheet, STM32L552VET6 pinout, STM32L552VET6 application, or STM32L552VET6 equivalent, key selection criteria include TrustZone-enabled peripheral isolation, SMPS vs LDO power mode tradeoffs, 114 GPIO count with independent supply options, and verified ULPMark-CP® (370) and SecureMark-TLS® (27400) benchmark scores.

Technical Context

The STM32L552VET6 implements a dual-core security architecture: the Cortex-M33 CPU executes in both Secure and Non-secure states, enforced by SAU and GTZC peripherals that partition memory, I/Os, and peripherals. Its ART Accelerator includes an 8-KB instruction cache enabling zero-wait-state execution from Flash at 110 MHz.

Power management combines three regulators-integrated LDO, embedded SMPS step-down converter, and external SMPS support-with seven low-power modes (Shutdown, Standby, Stop 2, etc.), where 17 nA Shutdown and 222 nA Standby with RTC are validated under specified VDD/VBAT conditions and temperature ranges.

Key Specifications

Pinout & Package

LQFP100 (14 × 14 mm, 0.5 mm pitch) package with exposed thermal pad; RoHS-compliant, industrial temperature grade (–40 °C to 125 °C).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar ultra-low-power secure MCU applications.

Compared with STM32U575ZIT6 and RA4M3GFP, the STM32L552VET6 uniquely balances sub-100 nA shutdown current, integrated SMPS, and production-proven TrustZone isolation-making it optimal for long-life, tamper-aware edge nodes where power budget dominates compute headroom.

Availability

STM32L552VET6 is available at Aetrix Electronics and suitable for industrial wireless sensors, secure medical wearables, smart utility meters, and asset tracking modules requiring stable component supply across extended temperature and lifecycle requirements.

Supply support for STM32L552VET6 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, designing and manufacturing microcontrollers, power management ICs, sensors, and automotive semiconductors.

The STM32L5 series targets secure, battery-operated IoT endpoints-combining Arm TrustZone, ultra-low-power design, and hardware root-of-trust to meet PSA Certified Level 3 and SESIP certification requirements.

FAQ

What is the maximum operating frequency and how is it achieved?

The STM32L552VET6 achieves 110 MHz maximum CPU frequency using its ART Accelerator's 8-KB instruction cache, which eliminates Flash wait states. This requires ICACHE enable and proper Flash latency configuration; actual sustained frequency depends on voltage scaling (range 1–3) and regulator mode (SMPS yields lower current per MHz than LDO).

Does STM32L552VET6 support external memory interfaces beyond OCTOSPI?

Yes-it integrates a Flexible Static Memory Controller (FSMC) supporting SRAM, PSRAM, NOR, NAND, and FRAM with address/data multiplexing. OCTOSPI complements this with high-speed x8/x4 serial interfaces, while FSMC provides parallel bus access for legacy or high-bandwidth external memory expansion.

How does TrustZone implementation differ from standard Cortex-M33 deployments?

STMicroelectronics extends standard TrustZone with GTZC (Global TrustZone Controller), enabling hardware-based peripheral attribution (e.g., assigning USART1 to Secure domain only) and memory region protection via SAU. Unlike generic implementations, GTZC allows runtime reconfiguration of secure/non-secure boundaries without CPU intervention.

What are the critical layout considerations for the embedded SMPS?

Layout must minimize loop area for PF0 (SMPS_EN), PF1 (SMPS_VOUT_SEL), and SMPS feedback pins; use dedicated ground planes under the SMPS section; place external inductor and capacitor per ST AN5250 guidelines; avoid routing sensitive analog traces near SMPS switching nodes to prevent coupling into VDDA or ADC references.