My Inquiry
My Account
STMicroelectronics STM32L562MEY6PTR
- Part No.:
- STM32L562MEY6PTR
- Manufacturer:
- STMicroelectronics
- Category:
- Microcontrollers
- Package:
- 81-UFBGA, WLCSP
- Datasheet:
-
STM32L562MEY6PTR.pdf
- Description:
- IC MCU 32BIT 512KB FLASH 81WLCSP
- Quantity:
- Payment:
- Shipping:
Inventory:4,940
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
STM32L562MEY6PTR from STMicroelectronics is an ultra-low-power Arm® Cortex®-M33 32-bit microcontroller with TrustZone® security, FPU, and SMPS support. It delivers 165 DMIPS at up to 110 MHz, integrates 512 KB Flash (dual-bank read-while-write), 256 KB SRAM (64 KB with hardware parity), and operates from 1.71 V to 3.6 V across –40°C to 125°C. It targets secure, battery-constrained edge nodes such as industrial wireless sensors and medical wearables requiring certified firmware integrity and sub-μA standby operation.
For engineers reviewing the STM32L562MEY6PTR datasheet, STM32L562MEY6PTR pinout, STM32L562MEY6PTR application, or STM32L562MEY6PTR equivalent, key selection criteria include TrustZone-enforced peripheral isolation, 222 nA Standby mode with RTC, AES+PKA cryptographic acceleration, Octo-SPI on-the-fly decryption, and dual-regulator (LDO/SMPS) power architecture for dynamic efficiency scaling.
Technical Context
The STM32L562MEY6PTR implements a dual-domain Arm Cortex-M33 core with hardware-enforced TrustZone separation between secure and non-secure worlds, enabling secure boot, runtime attestation, and isolated key storage in HDP. Its ART Accelerator includes an 8-KB instruction cache supporting zero-wait-state execution from Flash and external memories.
Power management integrates both an LDO and an SMPS step-down converter-enabling 62 μA/MHz active efficiency at 3 V-and supports Batch Acquisition Mode (BAM) for sensor data aggregation without CPU wake-up. The device features two independent 12-bit ADCs (5 Msps), two DACs, two op-amps with PGA, and three low-power timers available in Stop mode.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | Arm Cortex-M33 with TrustZone® and FPU - enables secure firmware partitioning and floating-point math for sensor fusion. |
| Max Clock Frequency | 110 MHz - achieves 165 DMIPS and 4.02 CoreMark®/MHz for real-time control in constrained environments. |
| Flash / SRAM | 512 KB Flash (dual-bank RWW), 256 KB SRAM (64 KB parity-protected) - supports safe over-the-air updates and fault-tolerant data buffering. |
| Low-Power Modes | 222 nA Standby with RTC, 3.16 μA Stop 2 with RTC, 5 μs wakeup - extends battery life in intermittent-sensing applications. |
| Cryptographic Engines | AES coprocessor, PKA (RSA/ECC), HASH, RNG (NIST SP800-90B compliant), OTFDEC - accelerates TLS handshake and encrypted firmware loading. |
| Analog Peripherals | 2× 12-bit ADC (5 Msps), 2× DAC, 2× op-amps with PGA, 2× comparators - enables local signal conditioning and closed-loop control without external ICs. |
| Communication Interfaces | 6× USART/LPUART, 4× I²C FM+, 3× SPI, 2× SAI, FDCAN, USB FS, UCPD, SDMMC, OCTOSPI - supports multi-protocol connectivity including USB-C PD and automotive CAN FD. |
Pinout & Package
STM32L562MEY6PTR is packaged in WLCSP81 (4.36 × 4.07 mm), a wafer-level chip-scale package optimized for space-constrained portable designs. It features 81 solder bumps with 0.4 mm pitch and ECOPACK2 environmental compliance.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD, VDDA, VDDIO2 | Power supply inputs | Dedicated domains for digital core (VDD), analog (VDDA), and I/O bank 2 (VDDIO2) - enable independent voltage scaling and noise isolation. |
| VSS, VSSA, VSSIO2 | Ground returns | Separate ground paths minimize coupling between digital switching noise and sensitive analog/sensor circuits. |
| NRST | Active-low reset input | Asynchronous reset with internal pull-up; supports external reset supervision and brownout detection in all modes except Shutdown. |
| PA0–PA15, PB0–PB15, etc. | General-purpose I/Os | Up to 114 fast GPIOs; most 5 V-tolerant, up to 14 with independent 1.08–3.6 V supply - support mixed-voltage interfacing and level-shifting reduction. |
| BOOT0 | Boot configuration | Controls boot source (system memory, embedded Flash, or SRAM); sampled at reset to determine initial vector fetch location. |
| VBAT | RTC/backup power | Supplies RTC and 32×32-bit backup registers at 187 nA - maintains timekeeping and critical state during main power loss. |
Key Features
| Feature | Design Value |
|---|---|
| TrustZone® + GTZC | Hardware-enforced secure/non-secure memory and peripheral partitioning - enables certified secure boot and runtime isolation of cryptographic keys and firmware assets. |
| SMPS + LDO dual regulator | 62 μA/MHz active current @ 3 V (SMPS mode) vs. 106 μA/MHz (LDO mode) - dynamically selectable for optimal efficiency across load conditions. |
| OCTOSPI + OTFDEC | On-the-fly decryption of external Octo-SPI memories using AES-128/256 - enables secure code execution from off-chip flash without exposing plaintext firmware. |
| ULPMark-CP® score | 370 - industry-standard benchmark confirming ultra-low-power performance in active and sleep cycles, validated per EEMBC methodology. |
| Secure Firmware Installation (SFI) | Root Secure Services (RSS)-based mechanism with embedded TF-M support - ensures authenticated, integrity-checked firmware updates without host dependency. |
Applications
| Industrial Wireless Sensor Node | Portable Medical Wearable |
|---|---|
|
Use Scenario: Battery-powered vibration/temperature node transmitting encrypted telemetry via LoRaWAN every 5 minutes. IC Role / Device Role / Timing Role: Main controller executing sensor fusion, TrustZone-secured crypto, and low-power scheduling with RTC-triggered wakeups. Use Value: 222 nA Standby + 5 μs wakeup enables >10-year coin-cell lifetime; OTFDEC allows secure firmware updates over air without exposing decrypted binaries. |
Use Scenario: ECG patch with continuous analog front-end sampling, real-time arrhythmia detection, and Bluetooth LE transmission. IC Role / Device Role / Timing Role: Signal processor running DSP algorithms on dual 12-bit ADCs, managing low-latency DAC feedback, and enforcing HIPAA-compliant data encryption. Use Value: Dual ADCs (5 Msps) capture high-fidelity biopotentials; PKA accelerates ECC-based signing of clinical data; 125°C rating supports sterilization cycles. |
| Smart Utility Meter | Secure IoT Gateway Edge Node |
|
Use Scenario: AMI meter with metrology ASIC interface, tamper detection, and NB-IoT backhaul under strict regulatory power budgets. IC Role / Device Role / Timing Role: Security co-processor handling SE-compliant key derivation, secure boot, and active tamper response (voltage/frequency/temp monitoring). Use Value: Active tamper detection and 96-bit unique ID meet IEC 62056 and ANSI C12.22 requirements; 17 nA Shutdown mode meets Class 0 meter quiescent current limits. |
Use Scenario: Field-deployable gateway aggregating Zigbee/Z-Wave sub-GHz traffic, performing TLS 1.3 termination, and forwarding to cloud via LTE. IC Role / Device Role / Timing Role: Secure application processor hosting TF-M, managing certificate lifecycle, and offloading AES/GCM and SHA-256 via hardware accelerators. Use Value: SecureMark-TLS® score of 27400 validates throughput for concurrent TLS sessions; UCPD + USB FS enables field service via USB-C with authenticated firmware recovery. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar ultra-low-power secure MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| STM32U575ZIT6Q | Higher clock (160 MHz), larger Flash (2 MB), no SMPS, uses LDO-only regulation; adds AI accelerator (ART AI) | Better suited for ML inference at edge; lacks sub-μA Stop 2 mode and OTFDEC - less optimal for long-life encrypted sensor nodes | Select when AI workload dominates and power budget allows >10× higher active current. |
| NXP LPC55S69JBD100 | Arm Cortex-M33, no TrustZone hardware partitioning, no SMPS, 640 KB Flash, 320 KB SRAM, no OTFDEC or PKA | Lacks certified secure boot and hardware crypto acceleration; requires software-only TLS stack - increases BOM cost and attack surface | Choose only if TrustZone and on-the-fly decryption are not required and cost sensitivity outweighs security certification needs. |
Compared with STM32U575ZIT6Q and LPC55S69JBD100, the STM32L562MEY6PTR uniquely balances sub-μA low-power operation, hardware-enforced TrustZone isolation, and integrated SMPS efficiency - making it the only option among the three qualified for ULPMark-CP®-certified, 10+ year battery life, and PSA Level 3-certified deployments.
Availability
STM32L562MEY6PTR is available at Aetrix Electronics and suitable for industrial wireless sensor nodes, portable medical wearables, smart utility meters, and secure IoT gateway edge nodes requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.
Supply support for STM32L562MEY6PTR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power management ICs, MEMS, and analog chips for industrial, automotive, and consumer markets.
The STM32L5 series is ST's flagship ultra-low-power secure MCU line, engineered specifically for battery-operated, safety-critical, and regulated-edge devices demanding PSA Certified Level 3, SESIP, and Common Criteria EAL4+ compliance.
FAQ
What is the maximum operating temperature range for STM32L562MEY6PTR?
The STM32L562MEY6PTR is rated for operation from –40°C to +125°C ambient temperature, validated per ST's industrial-grade qualification standards. This extended range supports deployment in harsh environments such as smart meters exposed to outdoor thermal cycling and medical devices undergoing autoclave sterilization.
Does STM32L562MEY6PTR support USB Type-C Power Delivery?
Yes - it integrates a dedicated USB Type-C™ and Power Delivery (UCPD) controller compliant with USB PD 3.0 specification. The UCPD peripheral handles BMC physical layer signaling, policy engine execution, and VCONN switching, enabling bidirectional power negotiation and role swapping without external PD controllers.
How is TrustZone® implemented in STM32L562MEY6PTR?
TrustZone is implemented via hardware-enforced memory and peripheral isolation using the Global TrustZone Controller (GTZC), SAU (Security Attribution Unit), and TZSC (TrustZone Security Configuration). It partitions Flash/SRAM into secure/non-secure banks and gates access to peripherals like RNG, AES, and PKA - all configurable at runtime via secure monitor calls.
What packaging options are available for STM32L562MEY6PTR besides WLCSP81?
The STM32L562MEY6PTR is exclusively offered in WLCSP81 (4.36 × 4.07 mm, 0.4 mm pitch). Other STM32L562 variants (e.g., STM32L562RET6) use LQFP64 or UFBGA132, but the Y6P suffix denotes this specific WLCSP81 configuration - no alternate packages exist for this orderable part number.
STM32L562MEY6PTR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Package/Case:
- 81-UFBGA, WLCSP
- Series:
- STM32L5
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- ARM® Cortex®-M33
- Core Size:
- 32-Bit Single-Core
- Speed:
- 110MHz
- Connectivity:
- CANbus, I2C, IrDA, LINbus, MMC/SD, QSPI, SAI, SPI, UART/USART, USB
- Peripherals:
- Brown-out Detect/Reset, DMA, PWM, WDT
- Number of I/O:
- 54
- Program Memory Size:
- 512KB (512K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 256K x 8
- Voltage - Supply (Vcc/Vdd):
- 1.71V ~ 3.6V
- Data Converters:
- A/D 16x12b; D/A 2x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
STM32L562MEY6PTR FAQ
1.How can I place an order for STM32L562MEY6PTR through Aetrix?
Please submit a Request for Quotation (RFQ) for STM32L562MEY6PTR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for STM32L562MEY6PTR reliable?
The price and inventory of STM32L562MEY6PTR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for STM32L562MEY6PTR is usually 5 days.
3.What payment methods are accepted for STM32L562MEY6PTR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for STM32L562MEY6PTR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for STM32L562MEY6PTR?
STM32L562MEY6PTR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your STM32L562MEY6PTR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for STM32L562MEY6PTR?
For technical support, including STM32L562MEY6PTR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your STM32L562MEY6PTR requirements.
6.How does Aetrix verify that STM32L562MEY6PTR is sourced from the original manufacturer or authorized distributors?
All STM32L562MEY6PTR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that STM32L562MEY6PTR meets industry standards.
7.What is the process for return or replacement of STM32L562MEY6PTR?
All STM32L562MEY6PTR units undergo pre-shipment inspection (PSI). If there is an issue with STM32L562MEY6PTR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The STM32L562MEY6PTR part is unused and in its original packaging.
Return procedure for STM32L562MEY6PTR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
STM32L562MEY6PTR Tags
-
ATTINY4-TSHR
Microchip Technology
-
ATTINY10-TSHR
Microchip Technology
-
ATTINY10-TS8R
Microchip Technology
-
ATTINY202-SSNR
Microchip Technology
-
ATTINY202-SSFR
Microchip Technology
-
ATTINY402-SSNR
Microchip Technology
-
PIC16F15213T-I/MF
Microchip Technology
-
PIC16F15213-E/MF
Microchip Technology
-
PIC10F200T-I/OT
Microchip Technology
-
ATTINY412-SSNR
Microchip Technology
-
PIC10F202T-I/OT
Microchip Technology
-
ATTINY404-SSNR
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
