STMicroelectronics STM32L562QEI6P
- Part No.:
- STM32L562QEI6P
- Manufacturer:
- STMicroelectronics
- Category:
- Microcontrollers
- Package:
- 132-UFBGA
- Datasheet:
-
STM32L562QEI6P.pdf
- Description:
- IC MCU 32BIT 512KB FLSH 132UFBGA
- Quantity:
- Payment:

- Shipping:

Inventory:2,728
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
STM32L562QEI6P from STMicroelectronics is an ultra-low-power Arm® Cortex®-M33 32-bit microcontroller with TrustZone® security, FPU, and SMPS support. It delivers 165 DMIPS at up to 110 MHz, integrates 512 KB Flash (dual-bank read-while-write), 256 KB SRAM (64 KB with hardware parity), and operates from 1.71 V to 3.6 V across –40°C to 125°C. It targets secure, battery-constrained IoT edge nodes requiring cryptographic acceleration (AES+PKA), real-time sensing, and low-power connectivity.
For engineers reviewing the STM32L562QEI6P datasheet, STM32L562QEI6P pinout, STM32L562QEI6P application, or STM32L562QEI6P equivalent, key selection criteria include TrustZone-enabled secure boot, sub-100 nA standby current with RTC, on-the-fly Octo-SPI decryption, ULPMark-CP® score of 370, and dual 12-bit ADCs with 5 Msps sampling.
Technical Context
The STM32L562QEI6P implements a dual-domain Arm Cortex-M33 core with separate secure/non-secure execution environments managed by TrustZone® and a Global TrustZone Controller (GTZC). Its FlexPowerControl architecture enables dynamic voltage scaling and mode transitions - including Shutdown (17 nA), Standby with RTC (222 nA), and Stop 2 (3.16 µA) - coordinated via embedded SMPS and LDO regulators.
Security is enforced through hardware root of trust (unique boot entry + HDP), SFI via embedded RSS, TF-M–compatible secure firmware upgrade, AES coprocessor, PKA, HASH accelerator, and active tamper detection. The ART Accelerator with 8 KB instruction cache ensures zero-wait-state execution from Flash at 110 MHz.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | Arm Cortex-M33 with TrustZone® and single-precision FPU - enables secure real-time processing and isolation of critical firmware assets. |
| Max Clock Frequency | 110 MHz - supports high-throughput sensor fusion and audio processing while maintaining sub-100 µA/MHz efficiency in SMPS mode. |
| Flash / SRAM | 512 KB dual-bank Flash (read-while-write), 256 KB SRAM (64 KB with parity) - allows safe over-the-air updates and ECC-protected data buffers. |
| Ultra-Low-Power Modes | 17 nA Shutdown, 222 nA Standby with RTC, 3.16 µA Stop 2 - extends multi-year battery life in metering and wearable applications. |
| Cryptographic Acceleration | AES-128/192/256, PKA (RSA/ECC), HASH (SHA-1/224/256), OTFDEC - offloads TLS handshake and encrypted external memory access from CPU. |
| Analog Peripherals | 2×12-bit ADC (5 Msps, 16-bit oversampling), 2×12-bit DAC, 2×OPAMP, 2×comparator - supports precision sensor signal chain without external components. |
| Communication Interfaces | FDCAN, USB 2.0 FS (crystal-less), UCPD, 6×USART/LPUART, 4×I²C, 3×SPI, 2×SAI, SDMMC - enables robust industrial and USB-C–enabled edge node connectivity. |
Pinout & Package
STM32L562QEI6P is packaged in UFQFPN48 (7 × 7 mm, 0.5 mm pitch), a lead-free, ECOPACK2-compliant quad flat no-lead package suitable for space-constrained PCB layouts and automated assembly.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD, VDDA, VDDIO2 | Digital/analog I/O supply rails | Independent 1.71–3.6 V domains enable mixed-signal integrity and flexible power sequencing. |
| VSS, VSSA | Digital/analog ground references | Separate analog/digital ground pins minimize noise coupling into ADC/DAC paths. |
| PA0–PA15, PB0–PB15, etc. | General-purpose I/Os (up to 114) | Most pins are 5 V-tolerant; up to 14 support independent 1.08–3.6 V supply for interfacing with low-voltage peripherals. |
| NRST | Active-low reset input | Asynchronous reset with internal pull-up; compatible with external supervisory circuits and brownout detection. |
| BOOT0 | Boot mode selection | Configures boot source (system memory, Flash, or SRAM); used during initial programming and recovery sequences. |
| VBAT | RTC and backup register supply | Accepts 1.65–3.6 V; maintains RTC calendar and 32×32-bit registers in 187 nA VBAT mode. |
| PC13–PC15 | RTC oscillator inputs/outputs | Supports 32.768 kHz crystal connection for ±20 ppm accuracy timing in all low-power modes. |
Key Features
| Feature | Design Value |
|---|---|
| TrustZone®-enabled secure boot | Hardware-enforced root of trust with unique boot entry and hide protection area (HDP) prevents unauthorized firmware execution. |
| On-the-fly Octo-SPI decryption (OTFDEC) | Enables secure execution directly from external encrypted flash without exposing decrypted code to system memory. |
| SMPS + LDO dual-regulator system | Reduces active-mode current to 62 µA/MHz @ 3 V - 42% lower than LDO-only operation - extending battery runtime significantly. |
| ULPMark-CP® score of 370 | Industry-standard benchmark confirming best-in-class energy efficiency for Cortex-M33-based MCUs in common workloads. |
| 165 DMIPS @ 110 MHz | Validated Dhrystone 2.1 performance metric enabling real-time control loops and lightweight ML inference at ultra-low power. |
Applications
| Smart Utility Metering | Wearable Health Monitor |
|---|---|
Use Scenario: Battery-powered gas/water/electricity meters transmitting encrypted consumption data hourly via NB-IoT or LoRaWAN. IC Role / Device Role / Timing Role: Main application processor executing secure firmware, managing crypto operations, and controlling metrology ADCs and RTC-critical time-stamping. Use Value: 17 nA Shutdown and 222 nA Standby with RTC enable >10-year battery life; AES+PKA accelerates TLS 1.2 handshakes without CPU overhead. | Use Scenario: Compact wrist-worn device continuously acquiring ECG, SpO₂, and motion data while maintaining Bluetooth LE connectivity. IC Role / Device Role / Timing Role: Central sensor hub performing analog front-end conditioning (OPAMP+ADC), real-time signal processing, and secure BLE packet encryption. Use Value: Dual 12-bit ADCs (5 Msps) capture high-fidelity biosignals; 3.16 µA Stop 2 mode preserves context during sensor sleep cycles with 5 µs wakeup latency. |
| Industrial Wireless Sensor Node | Secure USB-C Peripheral |
Use Scenario: Ruggedized environmental sensor node deployed in factory settings, measuring temperature, humidity, and vibration with periodic edge analytics. IC Role / Device Role / Timing Role: Low-power host MCU interfacing with MEMS sensors, running anomaly detection algorithms, and managing FDCAN or LPUART backhaul. Use Value: -40°C to 125°C extended temperature range ensures reliability; SMPS regulator sustains 62 µA/MHz efficiency across wide input voltage swings. | Use Scenario: Smart dock or accessory supporting USB Power Delivery negotiation, alternate mode display output, and firmware updates over USB-C. IC Role / Device Role / Timing Role: Dedicated UCPD controller managing PD policy engine, VCONN switching, and secure firmware installation (SFI) via embedded RSS. Use Value: Integrated UCPD peripheral eliminates external PD controller; SFI and TF-M support enable field-upgradable, cryptographically signed firmware images. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar ultra-low-power secure MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| STM32U575ZIT6 | Higher clock (160 MHz), larger Flash (2 MB), same TrustZone®/SMPS/AES/PKA, but no UCPD or FDCAN | Better suited for complex RTOS-based edge AI inference; lacks native USB-C PD and CAN FD support | Select when higher compute density and memory are required, and USB-C/automotive CAN are not needed. |
| NXP LPC55S69JBD100 | Arm Cortex-M33, 320 KB Flash, 256 KB SRAM, no SMPS, lower ultra-low-power performance (1.5 µA Stop mode) | Strong security (EdgeLock SE050 co-processor), but less optimized for multi-year battery operation | Prefer when hardware-backed secure element integration is prioritized over sub-µA low-power modes. |
Compared with STM32U575ZIT6 and LPC55S69JBD100, the STM32L562QEI6P uniquely balances sub-100 nA shutdown current, integrated UCPD, FDCAN, and on-the-fly Octo-SPI decryption - making it optimal for compact, long-life, USB-C–connected secure edge devices.
Availability
STM32L562QEI6P is available at Aetrix Electronics and suitable for smart metering, wearable health monitoring, industrial wireless sensor nodes, and secure USB-C peripherals requiring stable component supply and long-term lifecycle assurance.
Supply support for STM32L562QEI6P includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power management ICs, sensors, and analog products for industrial, automotive, and consumer markets.
The STM32L5 series is ST's flagship ultra-low-power secure MCU line, engineered specifically for battery-operated IoT endpoints demanding certified security (PSA Level 3), energy efficiency (ULPMark), and rich peripheral integration without external support chips.
FAQ
What is the maximum operating temperature for STM32L562QEI6P?
The STM32L562QEI6P is qualified for operation from –40°C to +125°C ambient temperature, meeting industrial and extended-temperature requirements. This rating is validated per ST's production test flow and applies to all package variants, including the UFQFPN48 used for this part number.
Does STM32L562QEI6P support hardware-based secure firmware updates?
Yes - it supports Secure Firmware Installation (SFI) via embedded Root Secure Services (RSS) and is compatible with Trusted Firmware-M (TF-M). Firmware images are cryptographically verified before execution using public-key acceleration (PKA) and AES-256 decryption, ensuring end-to-end update integrity.
Can STM32L562QEI6P execute code directly from external Octo-SPI flash?
Yes - with its On-the-Fly Decryption Engine (OTFDEC), the device can securely execute code from external encrypted Octo-SPI memories. Decryption occurs transparently in hardware, preventing plaintext exposure in system memory while maintaining deterministic real-time performance.
What debug interfaces are supported on STM32L562QEI6P?
The device supports Serial Wire Debug (SWD) and JTAG via its SWJ-DP interface, plus Embedded Trace Macrocell™ (ETM) for instruction-level tracing. All debug features remain accessible in non-secure mode; secure debug access requires proper TrustZone configuration and authentication.
STM32L562QEI6P Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Package/Case:
- 132-UFBGA
- Series:
- STM32L5
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- ARM® Cortex®-M33
- Core Size:
- 32-Bit Single-Core
- Speed:
- 110MHz
- Connectivity:
- CANbus, I2C, IrDA, LINbus, MMC/SD, QSPI, SAI, SPI, UART/USART, USB
- Peripherals:
- Brown-out Detect/Reset, DMA, PWM, WDT
- Number of I/O:
- 108
- Program Memory Size:
- 512KB (512K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 256K x 8
- Voltage - Supply (Vcc/Vdd):
- 1.71V ~ 3.6V
- Data Converters:
- A/D 16x12b; D/A 2x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
STM32L562QEI6P FAQ
1.How can I place an order for STM32L562QEI6P through Aetrix?
Please submit a Request for Quotation (RFQ) for STM32L562QEI6P on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for STM32L562QEI6P reliable?
The price and inventory of STM32L562QEI6P are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for STM32L562QEI6P is usually 5 days.
3.What payment methods are accepted for STM32L562QEI6P?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for STM32L562QEI6P transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for STM32L562QEI6P?
STM32L562QEI6P orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your STM32L562QEI6P order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for STM32L562QEI6P?
For technical support, including STM32L562QEI6P datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your STM32L562QEI6P requirements.
6.How does Aetrix verify that STM32L562QEI6P is sourced from the original manufacturer or authorized distributors?
All STM32L562QEI6P products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that STM32L562QEI6P meets industry standards.
7.What is the process for return or replacement of STM32L562QEI6P?
All STM32L562QEI6P units undergo pre-shipment inspection (PSI). If there is an issue with STM32L562QEI6P, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The STM32L562QEI6P part is unused and in its original packaging.
Return procedure for STM32L562QEI6P:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
STM32L562QEI6P Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…

