STMicroelectronics STM32MP131AAE3
- Part No.:
- STM32MP131AAE3
- Manufacturer:
- STMicroelectronics
- Category:
- Microprocessors
- Package:
- 289-LFBGA
- Datasheet:
-
STM32MP131AAE3.pdf
- Description:
- Linear IC's
- Quantity:
- Payment:

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Product details
Overview
STM32MP131AAE3 from STMicroelectronics is a dual-core Arm® Cortex®-A7 microprocessor operating up to 1 GHz, featuring 1× Gigabit Ethernet MAC (IEEE 1588v2), 1× 12-bit ADC (5 Msps), 24 timers, and hardware TrustZone® security. It integrates 128 KB L2 cache, 168 KB on-chip SRAM (128 KB AXI SYSRAM + 32 KB AHB SRAM + 8 KB backup SRAM), and supports LPDDR2/LPDDR3-1066 or DDR3/DDR3L-1066 external memory up to 1 Gbyte - deployed in industrial HMIs, edge gateways, and secure IoT edge nodes.
For engineers reviewing the STM32MP131AAE3 datasheet, STM32MP131AAE3 pinout, STM32MP131AAE3 application, or STM32MP131AAE3 equivalent, key selection considerations include its 289-ball LFBGA (14 × 14 mm, 0.8 mm pitch) package, dual-bus matrix architecture (64-bit AXI @ 266 MHz / 32-bit AHB @ 209 MHz), TrustZone-enabled peripheral isolation, and support for USB 2.0 HS Host + OTG simultaneously with SPDIF Rx (4 inputs) and dual SAI audio interfaces.
Technical Context
The STM32MP131AAE3 implements a heterogeneous dual-core Arm Cortex-A7 subsystem with NEON™ and TrustZone®, backed by 128 KB unified L2 cache and independent L1 I/D caches (32 KB each). Its memory subsystem includes dedicated DDR controller supporting LPDDR2/LPDDR3/DDR3/DDR3L at 1066 MT/s, plus dual Quad-SPI and flexible memory controller (FMC) for NAND/NOR/PSRAM expansion.
Security is enforced via TrustZone address space controller (TZC), embedded tamper detection (12 pins, 5 active), BSEC OTP control, and hardware accelerators including HASH (SHA-256/384/512), ECDSA verification, true RNG (6 triple oscillators), and DFSDM (4-channel sigma-delta filter). Clock management uses four fractional PLLs, internal HSI/CSI/LSI oscillators, and external HSE (8–48 MHz) and LSE (32.768 kHz) sources.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | Dual Arm Cortex-A7 @ up to 1 GHz with NEON and TrustZone - enables Linux-capable real-time processing with secure world/non-secure world partitioning. |
| L2 Cache | 128 KB unified - reduces external memory bandwidth pressure and improves deterministic latency for mixed workloads. |
| SRAM | 168 KB total: 128 KB AXI SYSRAM (low-latency system RAM), 32 KB AHB SRAM, 8 KB backup domain SRAM - supports fast boot, context retention, and RTC/calendar operation during VBAT mode. |
| External Memory | Up to 1 Gbyte DDR via 16-bit bus: LPDDR2/LPDDR3-1066 or DDR3/DDR3L-1066 - enables cost-optimized memory subsystem for Linux-based applications without requiring high-pin-count interfaces. |
| Ethernet | 1× IEEE 802.3-compliant GMAC with MII/RMII/RGMII and IEEE 1588v2 hardware timestamping - supports precise time synchronization in industrial automation and TSN-adjacent deployments. |
| ADC | 1× 12-bit SAR ADC up to 5 Msps with internal VREF+ buffer - suitable for analog sensor acquisition in motor control feedback loops and environmental monitoring. |
| Security | TrustZone peripherals, 12 tamper pins (5 active), BSEC OTP, HASH (SHA-256/384/512), ECDSA, true RNG - meets IEC 62443-3-3 SL2 requirements for secure boot and runtime attestation. |
| Package | LFBGA289 (14 × 14 mm, 0.8 mm pitch, B0ED marking) - RoHS-compliant, ECOPACK2, optimized for thermal dissipation and PCB routing density in compact edge devices. |
Pinout & Package
LFBGA289 (14 × 14 mm, 0.8 mm pitch, B0ED) package with 289 solder balls; compliant with JEDEC MO-270AB standard and ECOPACK2 environmental requirements.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDDCORE | Core power supply | 1.05–1.2 V supply for CPU and L1/L2 cache; requires low-noise regulation and local decoupling for stable 1 GHz operation. |
| VDDCPU | CPU voltage domain | Independent 0.8–1.2 V rail for Cortex-A7 cores; enables dynamic voltage scaling (DVS) to optimize power vs. performance. |
| VDDQ_DDR | DDR I/O supply | 1.2 V (LPDDR2/3) or 1.35 V (DDR3L) supply for DDR interface; must be sequenced after VDDCORE per power-up timing requirements. |
| NRST | Active-low reset input | Asynchronous reset pin with internal pull-up; asserts full system reset including CPU, peripherals, and debug logic upon falling edge. |
| BOOT0 | Boot mode selection | Strapped high/low at power-up to select boot source (FSMC, QSPI, SDMMC, USB, or UART) - critical for field firmware recovery and secure boot configuration. |
| ETH_MDC/MDIO | PHY management interface | IEEE 802.3 MDIO/MDC signals for configuring external Ethernet PHY registers - required for auto-negotiation and link status monitoring. |
Key Features
| Feature | Design Value |
|---|---|
| Arm TrustZone® System Protection | Hardware-enforced isolation between secure and non-secure worlds across memory, peripherals, and DMA - enables secure boot, encrypted firmware updates, and trusted execution environment (TEE) deployment. |
| Dual-Bus Interconnect Matrix | 64-bit AXI bus @ 266 MHz + 32-bit AHB bus @ 209 MHz - allows concurrent high-bandwidth data movement (e.g., video streaming over SAI while Ethernet packet processing occurs on AXI). |
| Audio Subsystem | 2× SAI (I2S/PDM/SPDIF Tx), SPDIF Rx (4 inputs), 5× SPI with I2S-class accuracy via audio PLL - supports multi-mic array processing, stereo playback, and professional audio I/O without external codecs. |
| Low-Power Strategy | Five low-power modes (Sleep, Stop, LPLV-Stop, LPLV-Stop2, Standby) with DDR retention in Standby - enables sub-100 µA system suspend current while preserving application state and network connectivity readiness. |
| Secure Debug Infrastructure | Arm CoreSight™ trace/debug with SWD/JTAG (reconfigurable as GPIOs), 4 KB embedded trace buffer, and debug authentication lock - balances development flexibility with production security enforcement. |
| Flexible Boot Options | Support for boot from QSPI, SDMMC, FSMC, USB, or UART with BSEC-managed OTP configuration - simplifies manufacturing provisioning and enables fallback recovery paths in deployed systems. |
Applications
| Industrial HMI | Edge Gateway |
|---|---|
Use Scenario: Touch-enabled factory floor display with real-time PLC communication and local data logging. IC Role / Device Role / Timing Role: Main application processor running Linux-based Qt UI, managing CAN/UART fieldbus bridges and local SQLite database writes. Use Value: Integrated 12-bit ADC and 24 timers enable direct analog sensor readout and PWM-controlled backlight dimming, reducing BOM count versus MCU+MPU hybrid architectures. | Use Scenario: Protocol-agnostic field gateway aggregating Modbus RTU, BACnet MS/TP, and LoRaWAN sensor data for cloud upload. IC Role / Device Role / Timing Role: Dual-core application processor executing containerized protocol stacks, with TrustZone isolating secure TLS offload and credential storage. Use Value: Hardware-accelerated SHA-256 and ECDSA verification ensures authenticated firmware updates and device identity binding without CPU overhead. |
| Secure IoT Node | Audio Edge Device |
Use Scenario: Tamper-evident smart meter with encrypted energy consumption reporting and remote firmware validation. IC Role / Device Role / Timing Role: Root-of-trust anchor with BSEC OTP fuses, active tamper pins monitoring enclosure integrity, and hardware RNG seeding secure key generation. Use Value: 12 tamper inputs (5 active) provide physical intrusion detection with sub-100 ms response latency, meeting ANSI C12.22 and DLMS/COSEM security mandates. | Use Scenario: Voice-controlled home assistant endpoint with far-field mic array, local wake-word detection, and low-latency audio playback. IC Role / Device Role / Timing Role: Audio subsystem controller handling PDM-to-I2S conversion via DFSDM, SAI-driven speaker output, and SPDIF Rx for multi-source digital audio ingestion. Use Value: Dual SAI interfaces and 4-channel DFSDM allow simultaneous 8-mic PDM capture and stereo I2S playback with <5 µs inter-channel skew - eliminating need for external audio DSP. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-core Arm Cortex-A7 microprocessor applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| STM32MP157A-DK1 | Higher-performance dual Cortex-A7 @ 800 MHz + Cortex-M4 coprocessor; 512 MB DDR support; additional GPU (Vivante GC7000Lite) | Targeted at GUI-rich applications (e.g., 720p display, OpenGL ES 2.0); larger footprint (TFBGA320) and higher power envelope | Select when GUI acceleration, M4 real-time co-processing, or >1 Gbyte DDR scalability is required - not drop-in compatible due to pinout and power sequencing differences. |
| i.MX 8M Mini (NXP) | Quad Cortex-A53 + Cortex-M4; supports LPDDR4; integrated MIPI DSI; lacks TrustZone-peripheral granularity and tamper pin count | Better suited for multimedia-centric designs (e.g., video conferencing endpoints); weaker hardware security certification path for industrial safety | Prefer for Android/Linux multimedia stacks needing MIPI-DSI or LPDDR4 bandwidth; avoid if tamper detection, BSEC OTP, or strict IEC 62443 compliance is mandatory. |
Compared with STM32MP131AAE3, the STM32MP157A-DK1 adds GUI acceleration and M4 co-processing at higher cost and power, while the i.MX 8M Mini offers broader multimedia IP but weaker hardware-rooted security primitives - making STM32MP131AAE3 optimal for cost-constrained, security-critical edge nodes where Cortex-A7 performance suffices.
Availability
STM32MP131AAE3 is available at Aetrix Electronics and suitable for industrial HMIs, secure IoT gateways, and audio edge devices requiring stable component supply, long-term lifecycle assurance, and qualified automotive-grade traceability.
Supply support for STM32MP131AAE3 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power ICs, sensors, and analog/mixed-signal products for industrial, automotive, and consumer markets.
The STM32MP series targets Linux-capable edge computing with hardware-enforced security, combining Cortex-A application processing with Cortex-M real-time capability - STM32MP131AAE3 specifically delivers cost-optimized, single-core-equivalent A7 performance with minimal package size and power for secure industrial edge nodes.
FAQ
What is the maximum supported DDR memory capacity and type for STM32MP131AAE3?
The STM32MP131AAE3 supports up to 1 Gbyte of external DDR memory via its 16-bit bus interface. Compatible memory types include LPDDR2/LPDDR3-1066 and DDR3/DDR3L-1066. The DDR controller implements hardware ECC and supports configurable burst lengths, refresh rates, and timing parameters per JEDEC standards - validated in ST's MP13-EV1 evaluation board design with Micron MT41K128M16JT-107 IT.
Does STM32MP131AAE3 include hardware cryptographic acceleration?
Yes. It integrates dedicated hardware accelerators including HASH (SHA-1/224/256/384/512, HMAC), ECDSA signature verification, a true random number generator (6 triple oscillators), and a CRC calculation unit. These blocks operate independently of the Cortex-A7 cores and are accessible via TrustZone-protected memory-mapped registers - enabling secure boot, TLS offload, and key derivation without software-only crypto overhead.
What are the key thermal and packaging specifications for the LFBGA289 variant?
The STM32MP131AAE3 in LFBGA289 (B0ED) has a 14 × 14 mm body size, 0.8 mm ball pitch, and JEDEC MO-270AB-compliant construction. Its θJA is 25.5 °C/W (4-layer PCB, 1 oz copper, 2 in² copper pour), with maximum junction temperature rated at 105 °C. The package uses lead-free, halogen-free ECOPACK2 materials and supports reflow profiles per IPC/JEDEC J-STD-020E.
How does the TrustZone implementation differ between STM32MP131AAE3 and earlier STM32MP15x devices?
Unlike STM32MP15x, which relies on external TZPC for peripheral protection, the STM32MP131AAE3 embeds TrustZone Address Space Controller (TZC) directly in the DDR controller and extends TrustZone protection to all peripherals via ETZPC - enabling fine-grained, register-level access control for each peripheral instance. It also adds 5 active tamper pins (vs. 3 in MP15x) and integrates BSEC OTP with 3072-bit fuses including 96-bit unique ID, strengthening root-of-trust capabilities for industrial certification.
STM32MP131AAE3 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Package/Case:
- 289-LFBGA
- Series:
- STM32MP1
- Packaging:
- Tray
- Product Status:
- Active
- Core Processor:
- ARM® Cortex®-A7
- Number of Cores/Bus Width:
- 1 Core, 32-Bit
- Speed:
- 650MHz
- Co-Processors/DSP:
- Multimedia; NEON™ SIMD
- RAM Controllers:
- DDR3, DDR3L, LPDDR2, LPDDR3
- Graphics Acceleration:
- Yes
- Display & Interface Controllers:
- LCD
- Ethernet:
- 10/100/1000Mbps (1)
- SATA:
- -
- USB:
- USB 2.0 (2)
- Voltage - I/O:
- 1.8V, 2.5V, 3.3V
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Security Features:
- AES, ARM TZ, Boot Security, Cryptography, Secure Debug, SHA-1/2, Tamper Detection, TRNG, Volatile key Storage
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 289-LFBGA (14x14)
- Additional Interfaces:
- GPIO, I2C, I2S, IrDA, MMC/SD/SDIO, SAI, SPDIF, SPI, UART/USART, USB
STM32MP131AAE3 FAQ
1.How can I place an order for STM32MP131AAE3 through Aetrix?
Please submit a Request for Quotation (RFQ) for STM32MP131AAE3 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for STM32MP131AAE3 reliable?
The price and inventory of STM32MP131AAE3 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for STM32MP131AAE3 is usually 5 days.
3.What payment methods are accepted for STM32MP131AAE3?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for STM32MP131AAE3 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for STM32MP131AAE3?
STM32MP131AAE3 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your STM32MP131AAE3 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for STM32MP131AAE3?
For technical support, including STM32MP131AAE3 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your STM32MP131AAE3 requirements.
6.How does Aetrix verify that STM32MP131AAE3 is sourced from the original manufacturer or authorized distributors?
All STM32MP131AAE3 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that STM32MP131AAE3 meets industry standards.
7.What is the process for return or replacement of STM32MP131AAE3?
All STM32MP131AAE3 units undergo pre-shipment inspection (PSI). If there is an issue with STM32MP131AAE3, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The STM32MP131AAE3 part is unused and in its original packaging.
Return procedure for STM32MP131AAE3:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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