STMicroelectronics STM32MP131AAF3

Overview

STM32MP131AAF3 from STMicroelectronics is a dual-core Arm® Cortex®-A7 microprocessor unit (MPU) operating up to 1 GHz, featuring TrustZone® security, 1× Gigabit Ethernet MAC (MII/RMII/RGMII), 1× 12-bit ADC (5 Msps), and 24 timers - deployed in industrial HMI, smart building gateways, and edge AI inference nodes requiring Linux-capable processing with real-time peripheral control.

For engineers reviewing the STM32MP131AAF3 datasheet, STM32MP131AAF3 pinout, STM32MP131AAF3 application, or STM32MP131AAF3 equivalent, key selection considerations include DDR3/LPDDR3 memory interface support, secure boot via BSEC and TrustZone peripherals, 135 GPIOs with tamper detection, and dual Quad-SPI for fast code execution from external flash.

Technical Context

The STM32MP131AAF3 integrates two Arm Cortex-A7 cores with L1 I/D caches (32 KB each), 128 KB unified L2 cache, NEON™ SIMD acceleration, and TrustZone®-enabled memory protection - enabling concurrent Linux user-space and real-time RTOS tasks on a single die. Its interconnect matrix comprises a 64-bit AXI bus (266 MHz) and 32-bit AHB bus (209 MHz), supporting deterministic latency for time-critical peripherals like SAI audio and SPDIF Rx.

Security is implemented at silicon level: 12 tamper pins (5 active), hardware-accelerated ECDSA verification, SHA-256/SHA-384/SHA-512 hashing, true RNG (6 triple oscillators), and secure RTC with sub-second accuracy - all managed by dedicated TrustZone address space controller (TZC) and embedded TrustZone protection controller (ETZPC).

Key Specifications

Pinout & Package

STM32MP131AAF3 is housed in a TFBGA289 package (9 × 9 mm, 0.5 mm pitch), compliant with ECOPACK2 environmental standards. Ball layout supports 135 secure GPIOs, dual Quad-SPI, DDR3/LPDDR3 interface (16-bit data bus), and dedicated power/ground distribution for noise-sensitive analog and high-speed digital domains.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar MPU applications.

Compared with STM32MP131AAF3, the STM32MP157C offers enhanced multimedia capability but increases BOM cost and thermal design complexity, while the i.MX 8M Mini delivers higher compute density at the expense of integrated hardware security - making STM32MP131AAF3 optimal for cost-sensitive, security-critical industrial edge nodes with modest display/audio needs.

Availability

STM32MP131AAF3 is available at Aetrix Electronics and suitable for industrial HMI gateways, smart building controllers, and edge AI vision nodes requiring stable component supply, long-term lifecycle support, and traceable sourcing for ISO 13485 and IEC 62443-certified designs.

Supply support for STM32MP131AAF3 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power ICs, sensors, and automotive-grade processors with over 48 years of industrial IP heritage.

The STM32MP series targets heterogeneous computing for industrial edge applications - combining Linux-capable application cores with real-time microcontroller subsystems and hardware security to replace FPGA+ARM SoC combinations in cost-sensitive, safety-aware deployments.

FAQ

What boot sources does the STM32MP131AAF3 support?

The STM32MP131AAF3 supports boot from eMMC, SD card, Quad-SPI NOR/NAND flash, and parallel NAND via its flexible boot ROM. Boot mode is selected using BOOT0/BOOT1 pins, and secure boot is enforced through BSEC OTP fuses and TrustZone-protected first-stage bootloader (FSBL) validation.

Does the STM32MP131AAF3 include an integrated Ethernet PHY?

No, the STM32MP131AAF3 integrates only the Ethernet MAC/GMAC layer (IEEE 1588v2 compliant) and requires an external PHY chip for physical layer signaling. It supports MII, RMII, and RGMII interfaces with programmable delay compensation for trace-length matching in 4-layer PCB layouts.

How is DDR memory retention managed during low-power modes?

In Standby mode, the STM32MP131AAF3 maintains DDR SDRAM contents using self-refresh while powering down CPU cores, caches, and most peripherals. The DDR controller retains configuration, and wakeup restores full operation within 1.2 ms - verified per DS13878 Rev 7 Section 6.3.7.

What is the maximum supported clock frequency for the QUADSPI interface?

The QUADSPI interface operates up to 133 MHz in double-data-rate (DDR) mode, delivering 1.064 Gbit/s throughput. This is achieved using the internal audio PLL or external clock source, with configurable latency cycles and dummy cycles per DS13878 Rev 7 Section 6.3.20.