STMicroelectronics STM32MP131CAE3

Overview

STM32MP131CAE3 from STMicroelectronics is a dual-core Arm® Cortex®-A7 microprocessor unit (MPU) operating up to 1 GHz, featuring integrated TrustZone® security, 1× Gigabit Ethernet MAC, 1× 12-bit ADC (5 Msps), hardware crypto acceleration (AES-128/192/256, SHA-256/512, PKA), and support for LPDDR3-1066/DDR3L-1066 external memory - deployed in industrial HMI gateways requiring secure Linux-based edge processing.

For engineers reviewing the STM32MP131CAE3 datasheet, STM32MP131CAE3 pinout, STM32MP131CAE3 application, or STM32MP131CAE3 equivalent, key selection considerations include DDR controller timing compliance, TrustZone peripheral partitioning, Ethernet IEEE 1588v2 hardware timestamping, and secure boot chain validation using BSEC and tamper pins.

Technical Context

The STM32MP131CAE3 implements a dual-bus interconnect architecture with a 64-bit AXI matrix (266 MHz) and 32-bit AHB matrix (209 MHz), enabling concurrent high-bandwidth data movement between CPU, DMA controllers (MDMA + 3 dual-port DMAs), and peripherals including dual SDMMC, SAI, SPDIFRX, and QUADSPI. Its memory subsystem integrates 128 KB AXI SYSRAM, 32 KB AHB SRAM, and 8 KB backup SRAM with retention during Standby mode.

Security is enforced via Arm TrustZone®, ETZPC address space protection, TZC for DDR, BSEC OTP control, 12 tamper pins (5 active), and hardware-accelerated cryptographic engines (SAES, PKA, HASH, RNG) - all coordinated through a dedicated secure boot ROM and secure RTC with sub-second accuracy.

Key Specifications

Pinout & Package

STM32MP131CAE3 uses a TFBGA289 (9 × 9 mm, 0.5 mm pitch) package with 289 I/O balls. Pin functions are defined per ball position in ST's DS13877 Rev 7 (Section 4), supporting multiple alternate functions (AF0–AF15) across GPIO banks A–K. Key signal groups include DDR interface (DQ[15:0], DQS, CK, CKE), Ethernet (ETH_MDC, ETH_MDIO, ETH_RXD[3:0], ETH_TXD[3:0]), and secure debug (SWDIO, SWCLK).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar MPU applications.

Compared with NXP i.MX 8M Mini and Renesas RZ/G2L, STM32MP131CAE3 delivers superior hardware-enforced security granularity (12 tamper pins, TZC+ETZPC DDR protection, BSEC fuses) and deterministic Ethernet timing (1588v2 hardware timestamps), making it optimal for safety-certified industrial gateways where firmware integrity and protocol determinism are non-negotiable.

Availability

STM32MP131CAE3 is available at Aetrix Electronics and suitable for industrial HMI gateways, secure edge IoT nodes, medical diagnostic terminals, and automated test equipment requiring stable component supply across multi-year production cycles.

Supply support for STM32MP131CAE3 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power management ICs, sensors, and analog products for industrial, automotive, and consumer markets.

The STM32MP series targets heterogeneous Linux-capable applications requiring real-time responsiveness, hardware security, and low-power operation - specifically engineered for industrial edge devices needing certified secure boot and deterministic communication stacks.

FAQ

What boot sources does STM32MP131CAE3 support?

STM32MP131CAE3 supports boot from SDMMC, eMMC, Quad-SPI NOR/NAND flash, USB device (DFU mode), UART (for recovery), and FSMC-connected parallel memories. Boot mode is selected via BOOT0/BOOT1 pins at power-on reset, with fallback to serial loader if primary source fails - all verified by secure ROM bootloader before loading FSBL.

Does STM32MP131CAE3 require an external PMIC?

Yes - STM32MP131CAE3 requires an external PMIC (e.g., STPMIC1) to generate its multiple voltage rails: VDDCORE (0.8–1.1 V), VDDCPU (0.8–1.1 V), VDD_DDR (1.2/1.35 V), VDDIO (1.71–3.6 V), and VDDUSB (1.8 V). The on-chip LDOs only provide USB PHY (1.8 V) and core (1.1 V) regulation; full power sequencing and dynamic voltage scaling depend on companion PMIC control.

How is TrustZone implemented on STM32MP131CAE3?

TrustZone is implemented via Arm-defined secure monitor, TZC-400 DDR controller, ETZPC peripheral protection, and secure boot ROM enforcing authenticated firmware images. All peripherals are assigned secure/non-secure attributes in ETZPC; DDR accesses are filtered by TZC; and secure world execution is isolated using NS bit in SCR register - verified at every exception entry/exit.

What is the maximum DDR bandwidth achievable with STM32MP131CAE3?

With LPDDR3-1066 (533 MHz clock, 16-bit bus), STM32MP131CAE3 achieves up to 1.7 GB/s peak theoretical bandwidth. Real-world sustained bandwidth depends on AXI bus arbitration, DDR PHY tuning (per DS13877 Section 6.3.13), and memory controller configuration - measured at 1.2 GB/s in ST reference designs using dual-rank LPDDR3 with optimized refresh and precharge settings.