STMicroelectronics STM32MP131CAF3

Overview

STM32MP131CAF3 from STMicroelectronics is a dual-core Arm® Cortex®-A7 microprocessor unit (MPU) operating up to 1 GHz, featuring integrated TrustZone® security, 1× Gigabit Ethernet MAC (MII/RMII/RGMII), 1× 12-bit ADC (5 Msps), and hardware crypto acceleration (AES-128/192/256, SHA-256/512, PKA). It targets secure industrial HMI, edge gateway, and smart appliance control systems requiring real-time Linux-capable processing with deterministic I/O.

For engineers reviewing the STM32MP131CAF3 datasheet, STM32MP131CAF3 pinout, STM32MP131CAF3 application, or STM32MP131CAF3 equivalent, key selection considerations include its LFBGA289 (14 × 14 mm, 0.8 mm pitch) package, dual-bus matrix architecture (AXI @ 266 MHz / AHB @ 209 MHz), DDR3/LPDDR3 memory controller supporting up to 1 Gbyte, and TrustZone-enabled peripheral isolation for secure boot and tamper monitoring.

Technical Context

The STM32MP131CAF3 implements a heterogeneous dual-core Arm Cortex-A7 subsystem with unified 128-Kbyte L2 cache, NEON™ SIMD support, and TrustZone®-enabled memory protection. Its interconnect comprises a 64-bit AXI bus matrix (266 MHz) and 32-bit AHB matrix (209 MHz), enabling concurrent high-bandwidth peripheral access and low-latency CPU-to-SRAM paths.

Security is enforced via hardware-based mechanisms: BSEC OTP fuses (3072-bit, including 96-bit UID and 256-bit HUK), ETZPC peripheral firewall, TZC DDR address space controller, and 12 tamper pins (5 active). Power management includes five low-power modes (Sleep, Stop, LPLV-Stop, LPLV-Stop2, Standby) with DDR retention in Standby and backup regulator (~0.9 V) for RTC domain operation.

Key Specifications

Pinout & Package

LFBGA289 (B0ED) package: 289-ball grid array, 14 × 14 mm body, 0.8 mm ball pitch, RoHS-compliant ECOPACK2 finish. Ball layout supports full peripheral routing including dual DDR interface, Gigabit Ethernet PHY signals, and dedicated TrustZone-protected I/O banks.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar MPU applications.

Compared with STM32MP131CAF3, the STM32MP157C-DK2 adds GPU and USB 3.0 but increases BOM cost and thermal footprint, while the i.MX 8M Mini offers higher CPU throughput but lacks tamper detection and TrustZone peripheral enforcement-critical for industrial security certification.

Availability

STM32MP131CAF3 is available at Aetrix Electronics and suitable for industrial HMI, smart home gateways, edge AI sensor nodes, and secure PLC controllers requiring stable component supply across multi-year production cycles.

Supply support for STM32MP131CAF3 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, specializing in microcontrollers, power management, sensors, and automotive ICs with strong focus on industrial and embedded markets.

The STM32MP series is ST's Linux-capable MPU product line designed specifically for resource-constrained edge applications requiring real-time responsiveness, hardware security, and long-term availability-targeting industrial automation, building control, and smart infrastructure.

FAQ

What boot sources does the STM32MP131CAF3 support?

The STM32MP131CAF3 supports boot from multiple sources including eMMC/SD card, Quad-SPI NOR flash, NAND flash (with 8-bit ECC), and USB mass storage. Boot mode is selected via BOOT0 and BOOT1 pins per Table 2 in DS13877 Rev 7, with fallback to system memory if primary source fails. Secure boot validates signed images using keys stored in OTP fuses.

Does the STM32MP131CAF3 include hardware debug support?

Yes-it integrates Arm CoreSight™ debug infrastructure with SWD and JTAG interfaces usable as GPIOs when not in debug mode. It includes a 4-Kbyte embedded trace buffer and supports secure debug authentication via TrustZone. JTAG/SWD electrical characteristics are specified in Section 6.3.36 of DS13877 Rev 7.

How is DDR memory retention managed during low-power modes?

In Standby mode, the STM32MP131CAF3 maintains DDR SDRAM contents using its backup regulator (~0.9 V) and dedicated DDR self-refresh controller. This enables sub-100 μs wake-up while preserving full application state-verified in Section 6.3.7 (Table 28) and Section 3.7 of DS13877 Rev 7.

What is the maximum resolution and sampling rate of the integrated ADC?

The STM32MP131CAF3 features one 12-bit successive approximation register (SAR) ADC with maximum resolution of 12 bits and sampling rate up to 5 Msps. It supports internal or external VREF+ reference, programmable sampling time, and DMA-triggered conversions-fully characterized in Section 6.3.22 of DS13877 Rev 7.