My Inquiry
My Account
STMicroelectronics STM32MP131CAG3
- Part No.:
- STM32MP131CAG3
- Manufacturer:
- STMicroelectronics
- Category:
- Microprocessors
- Package:
- 289-TFBGA
- Datasheet:
-
STM32MP131CAG3.pdf
- Description:
- Linear IC's
- Quantity:
- Payment:
- Shipping:
Inventory:1,747
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
STM32MP131CAG3 from STMicroelectronics is a dual-core Arm® Cortex®-A7 microprocessor operating up to 1 GHz, featuring TrustZone® security, 1× Gigabit Ethernet MAC (MII/RMII/RGMII), 1× 12-bit ADC (5 Msps), and hardware crypto acceleration (AES-128/192/256, SHA-256/384/512, PKA). It targets secure industrial HMI, edge gateway, and smart building controller applications requiring real-time Linux-capable processing with integrated safety monitoring.
For engineers reviewing the STM32MP131CAG3 datasheet, STM32MP131CAG3 pinout, STM32MP131CAG3 application, or STM32MP131CAG3 equivalent, key selection considerations include DDR3/LPDDR3 memory interface support, 135 secure GPIOs with tamper detection, TrustZone-enabled peripheral isolation, and dual-PLL clock architecture for deterministic audio/video timing.
Technical Context
The STM32MP131CAG3 integrates two Arm Cortex-A7 cores with L1 I/D cache (32 KB each) and unified 128 KB L2 cache, NEON SIMD support, and TrustZone-based memory protection enforced by TZC and ETZPC controllers. Its interconnect uses a 64-bit AXI bus matrix (266 MHz) and 32-bit AHB matrix (209 MHz) to coordinate CPU, DMA, and peripherals.
Security is implemented at silicon level: secure boot chain, 12 tamper pins (5 active), 3072-bit OTP fuses (including 256-bit HUK), on-the-fly AES-128 DRAM encryption, and DPA-resistant PKA/ECC/RSA acceleration. Power management includes five low-power modes (LPLV-Stop2, Standby with DDR retention) and internal LDOs for USB PHY (1.8 V) and core (1.1 V).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | Arm Cortex-A7 dual-core, up to 1 GHz - enables Linux RTOS execution with deterministic interrupt latency |
| Memory Interface | LPDDR2/LPDDR3-1066 or DDR3/DDR3L-1066, 16-bit bus - supports up to 1 Gbyte external SDRAM for embedded Linux workloads |
| Security Features | TrustZone®, secure boot, 12 tamper pins, 256-bit HUK, AES-128 DRAM encryption - meets IEC 62443-3-3 SL2 requirements for industrial control |
| Analog Peripherals | 1× 12-bit ADC (5 Msps), 1× temperature sensor, DFSDM (4-channel sigma-delta filter) - enables high-fidelity sensor fusion in predictive maintenance systems |
| Communication Interfaces | 2× USB 2.0 HS (Host + OTG), 1× Ethernet MAC (IEEE 1588v2), 5× I2C, 4× UART/USART, 5× SPI - supports multi-protocol fieldbus bridging (Modbus TCP, CAN over USB) |
| Timers & Watchdogs | 24 timers including 2× 32-bit general-purpose, 10× 16-bit GP, 5× LP, RTC with sub-second accuracy - provides precise scheduling for time-sensitive automation tasks |
| Package | TFBGA289 (9 × 9 mm, 0.5 mm pitch) - compact footprint compatible with automated SMT assembly and thermal pad reflow profiles |
Pinout & Package
STM32MP131CAG3 is housed in a TFBGA289 package (9 × 9 mm, 0.5 mm pitch), RoHS-compliant and ECOPACK2 certified. The ball grid includes dedicated power domains (VDDCORE, VDDIO, VDDQ_DDR), multiple ground planes, and configurable I/O banks supporting 5 V-tolerant operation.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDDCORE | Core power supply | 1.1 V ±5% supply for CPU and L2 cache; requires low-noise decoupling per ST AN5210 |
| VDDIO | I/O power supply | 1.71–3.6 V supply enabling 5 V-tolerant GPIOs; supports mixed-voltage system interfacing |
| VDDQ_DDR | DDR I/O supply | 1.2 V or 1.35 V supply for DDR3/LPDDR3 interface; critical for signal integrity in 1066 MT/s operation |
| NRST | Active-low reset input | Asynchronous reset with internal pull-up; debounced via external RC network per DS13877 §6.3.18 |
| BOOT0 | Boot mode selection | High at power-up selects internal Flash boot; tied low for SDMMC/USB boot - defines initial firmware load path |
| ETH_MDC/MDIO | Ethernet management interface | IEEE 802.3-compliant MDIO bus for PHY configuration; supports auto-negotiation and link status polling |
Key Features
| Feature | Design Value |
|---|---|
| Dual Cortex-A7 with L2 cache | Enables concurrent Linux user-space and real-time RTOS tasks without external co-processor |
| TrustZone address space controller (TZC) | Hardware-enforced memory partitioning between secure/non-secure worlds for firmware update integrity |
| On-chip LDOs (1.1 V, 1.8 V) | Eliminates need for external PMIC in cost-sensitive gateways; reduces BOM count by ≥3 components |
| DFSDM with 4 channels | Direct sigma-delta modulator interface for high-resolution current/voltage sensing in motor drives |
| USB 2.0 HS Host + OTG | Simultaneous peripheral attachment (e.g., camera) and host-mode device enumeration (e.g., USB flash drive) |
| Standby mode with DDR retention | Sub-100 µA wake-up capable state preserving full RAM context - ideal for battery-backed edge nodes |
Applications
| Industrial HMI Controller | Smart Building Gateway |
|---|---|
Use Scenario: Touchscreen-based HVAC control panel with local logic and cloud telemetry. IC Role / Device Role / Timing Role: Main application processor executing Yocto Linux, managing display framebuffer, Ethernet backhaul, and secure OTA updates. Use Value: Integrated TrustZone and AES-128 DRAM encryption protect firmware and sensor data against physical tampering and memory scraping attacks. |
Use Scenario: Multi-protocol building automation hub connecting BACnet MS/TP, Modbus RTU, and KNX devices to MQTT cloud broker. IC Role / Device Role / Timing Role: Protocol translation engine using dual USB HS ports for legacy fieldbus adapters and Ethernet for IP backbone. Use Value: 135 secure GPIOs with 5 active tampers enable tamper-evident enclosure monitoring and secure boot enforcement across distributed nodes. |
| Edge AI Vision Node | Secure Industrial PLC |
Use Scenario: Low-power vision inference node performing object detection on 720p video streams using TensorFlow Lite Micro. IC Role / Device Role / Timing Role: Real-time inference accelerator leveraging NEON SIMD and 128 KB L2 cache for frame buffering and model execution. Use Value: Dual Quad-SPI interfaces allow parallel boot from one flash and firmware storage on another - enabling A/B firmware updates without downtime. |
Use Scenario: Safety-monitored programmable logic controller with watchdog supervision and voltage/frequency monitoring. IC Role / Device Role / Timing Role: Deterministic control engine running IEC 61131-3 runtime with secure RTC and sub-second timestamping for event logging. Use Value: Internal temperature/voltage/frequency monitors feed into hardware watchdogs, enabling autonomous fail-safe shutdown before thermal runaway or brownout. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-core Arm A-class microprocessor applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| NXP i.MX 8M Mini (LQM) | Quad-core Cortex-A53 + Cortex-M4; higher compute throughput but larger package (14 × 14 mm) and no integrated DDR LDOs | Better for multimedia-rich UIs; less suitable for space-constrained industrial enclosures | Select when >1.5 GHz CPU performance and GPU offload are required; avoid if BOM cost and PCB area are primary constraints |
| Renesas RZ/G2L | Single Cortex-A55 + Cortex-M33; lower power (300 mW typical), no TrustZone-peripheral isolation, only 1× USB 2.0 HS | Targeted at ultra-low-power remote I/O modules; lacks IEEE 1588v2 Ethernet support | Select for battery-operated edge sensors needing <100 µA standby; avoid for time-critical industrial networking |
Compared with i.MX 8M Mini and RZ/G2L, the STM32MP131CAG3 delivers optimal balance of TrustZone security granularity, integrated power regulation, and compact TFBGA289 packaging - making it uniquely suited for cost-sensitive, security-critical industrial gateways where board space and supply-chain simplicity are design priorities.
Availability
STM32MP131CAG3 is available at Aetrix Electronics and suitable for industrial HMI, smart building gateways, and edge AI vision nodes requiring stable component supply across extended product lifecycles.
Supply support for STM32MP131CAG3 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, specializing in microcontrollers, power management, and automotive ICs with over 40 years of industrial-grade reliability heritage.
The STM32MP series was designed specifically for Linux-capable embedded applications demanding hardware-enforced security, real-time responsiveness, and seamless integration with industrial communication stacks - bridging the gap between microcontrollers and application processors.
FAQ
What boot sources does the STM32MP131CAG3 support?
The STM32MP131CAG3 supports boot from internal Flash (via embedded ROM code), SDMMC (eMMC/SDIO), USB mass storage, and Quad-SPI NOR flash. Boot mode is selected via BOOT0 and BOOT1 pins at power-on reset, with configuration stored in OTP fuses for permanent lockdown in production units.
Does the STM32MP131CAG3 include hardware cryptographic accelerators?
Yes - it integrates dedicated hardware blocks for AES-128/192/256 encryption/decryption, SHA-224/256/384/512 hashing, HMAC, PKA (ECC/RSA with DPA protection), and a true random number generator (TRNG) with three independent oscillators. These operate independently of the CPU cores to accelerate secure boot and TLS stack operations.
What is the maximum DDR memory bandwidth supported?
The STM32MP131CAG3 DDR controller supports LPDDR2/LPDDR3-1066 and DDR3/DDR3L-1066 at 16-bit bus width, delivering up to 2.1 GB/s theoretical bandwidth. Actual sustained bandwidth depends on layout quality, termination, and memory vendor timing parameters per JEDEC JESD209-3 specification.
How many secure GPIOs are available and what tamper features do they support?
The device provides up to 135 secure GPIOs with interrupt capability and six dedicated wakeup lines. Twelve pins are designated as tamper inputs, including five active-tamper pins that trigger immediate secure erase of OTP keys and force system reset upon voltage/current/edge violation - meeting IEC 62443-3-3 tamper detection requirements.
STM32MP131CAG3 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Package/Case:
- 289-TFBGA
- Series:
- STM32MP1
- Packaging:
- Tray
- Product Status:
- Active
- Core Processor:
- ARM® Cortex®-A7
- Number of Cores/Bus Width:
- 1 Core, 32-Bit
- Speed:
- 650MHz
- Co-Processors/DSP:
- Multimedia; NEON™ SIMD
- RAM Controllers:
- DDR3, DDR3L, LPDDR2, LPDDR3
- Graphics Acceleration:
- Yes
- Display & Interface Controllers:
- LCD
- Ethernet:
- 10/100/1000Mbps (1)
- SATA:
- -
- USB:
- USB 2.0 (2)
- Voltage - I/O:
- 1.8V, 2.5V, 3.3V
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Security Features:
- AES, ARM TZ, Boot Security, Cryptography, Secure Debug, SHA-1/2, Tamper Detection, TRNG, Volatile key Storage
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 289-TFBGA (9x9)
- Additional Interfaces:
- GPIO, I2C, I2S, IrDA, MMC/SD/SDIO, SAI, SPDIF, SPI, UART/USART, USB
STM32MP131CAG3 FAQ
1.How can I place an order for STM32MP131CAG3 through Aetrix?
Please submit a Request for Quotation (RFQ) for STM32MP131CAG3 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for STM32MP131CAG3 reliable?
The price and inventory of STM32MP131CAG3 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for STM32MP131CAG3 is usually 5 days.
3.What payment methods are accepted for STM32MP131CAG3?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for STM32MP131CAG3 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for STM32MP131CAG3?
STM32MP131CAG3 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your STM32MP131CAG3 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for STM32MP131CAG3?
For technical support, including STM32MP131CAG3 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your STM32MP131CAG3 requirements.
6.How does Aetrix verify that STM32MP131CAG3 is sourced from the original manufacturer or authorized distributors?
All STM32MP131CAG3 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that STM32MP131CAG3 meets industry standards.
7.What is the process for return or replacement of STM32MP131CAG3?
All STM32MP131CAG3 units undergo pre-shipment inspection (PSI). If there is an issue with STM32MP131CAG3, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The STM32MP131CAG3 part is unused and in its original packaging.
Return procedure for STM32MP131CAG3:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
STM32MP131CAG3 Tags
-
AT91SAM9260B-CU-999
Microchip Technology
-
AT91SAM9G25-CU
Microchip Technology
-
ATSAMA5D27C-CU
Microchip Technology
-
AT91SAM9X35-CU
Microchip Technology
-
AT91SAM9X25-CU
Microchip Technology
-
MCIMX6Y2CVM08AB
NXP Semiconductors
.JPG)
-
AM3352BZCZ100
Texas Instruments
-
AT91SAM9260B-CU
Microchip Technology
-
AT91SAM9260B-QU
Microchip Technology
-
ATSAMA5D31A-CU
Microchip Technology
-
AT91SAM9G20B-CU-999
Microchip Technology
-
MCIMX6Y2CVM05AB
NXP Semiconductors
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
