STMicroelectronics STM32MP131CAG3T

Overview

STM32MP131CAG3T from STMicroelectronics is a dual-core Arm® Cortex®-A7 microprocessor unit (MPU) operating up to 1 GHz, featuring TrustZone® security, 1× Gigabit Ethernet MAC, 1× 12-bit ADC (5 Msps), and hardware crypto acceleration (AES-128/192/256, SHA-256/512, PKA). It targets secure industrial HMI, edge gateway, and smart appliance control where real-time Linux execution, peripheral integration, and tamper-resistant boot are required.

For engineers reviewing the STM32MP131CAG3T datasheet, STM32MP131CAG3T pinout, STM32MP131CAG3T application, or STM32MP131CAG3T equivalent, key selection considerations include DDR3/LPDDR3 memory controller timing, TrustZone® peripheral partitioning, Ethernet IEEE 1588v2 support, and LFBGA289 (14 × 14 mm, 0.8 mm pitch) mechanical compatibility with thermal and signal integrity constraints.

Technical Context

The STM32MP131CAG3T implements a dual-bus matrix architecture: a 64-bit AXI interconnect (266 MHz) for high-bandwidth CPU–DDR traffic and a 32-bit AHB interconnect (209 MHz) for peripheral access. Its Cortex-A7 cores include L1 I/D caches (32 KB each) and a shared 128 KB L2 cache, with NEON™ for DSP workloads and TrustZone® for secure/non-secure world isolation.

Security is enforced via BSEC OTP fuses (3072-bit, including 96-bit UID and 256-bit HUK), dedicated tamper pins (12 total, 5 active), secure RTC, and hardware-accelerated AES on-the-fly DRAM encryption. Boot flow enforces signed image verification before execution in secure mode.

Key Specifications

Pinout & Package

LFBGA289 package (14 × 14 mm, 0.8 mm pitch, B0ED variant), RoHS-compliant and ECOPACK2-certified. Ball grid includes dedicated power domains (VDDCORE, VDDCPU, VDDQ_DDR), 135 secure GPIOs with wakeup capability, and dedicated DDR interface lanes (DQ[15:0], DQS[1:0], DM[1:0], CK/CK#, CKE, CS#, RAS#, CAS#, WE#).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar MPU-based embedded Linux applications.

Compared with i.MX 8M Mini and RZ/G2L, the STM32MP131CAG3T delivers optimal balance of security depth (OTP fuses, active tampers, TrustZone®-enforced peripheral isolation), compact LFBGA289 footprint, and verified low-power operation-making it ideal for cost-sensitive, certifiable industrial edge nodes where security assurance outweighs raw CPU performance.

Availability

STM32MP131CAG3T is available at Aetrix Electronics and suitable for industrial HMI, smart home edge controllers, medical diagnostic terminals, and energy meter data concentrators requiring stable component supply across multi-year production cycles.

Supply support for STM32MP131CAG3T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power management ICs, sensors, and automotive semiconductors with vertical fabrication capacity.

The STM32MP series is ST's heterogeneous MPU product line targeting Linux-capable edge devices with integrated security, real-time responsiveness, and industrial-grade reliability-designed specifically for applications demanding both application-level OS functionality and hardware-enforced trust boundaries.

FAQ

What boot sources does the STM32MP131CAG3T support?

The STM32MP131CAG3T supports boot from internal Flash (via embedded ROM loader), eMMC/SD card, Quad-SPI NOR/NAND, and parallel NAND via Flexible Memory Controller. Boot mode is selected by BOOT0 and BOOT1 pins at power-up, with secure boot enforcing digital signature verification for all external sources using keys stored in BSEC OTP fuses.

Does the STM32MP131CAG3T include hardware support for IEEE 1588 Precision Time Protocol?

Yes-the integrated Ethernet MAC includes full IEEE 1588v2 hardware timestamping with sub-10 ns resolution, supporting PTP master/slave operation, transparent clock, and boundary clock modes. Timestamp registers are accessible via memory-mapped registers and synchronized to the system clock domain for deterministic latency.

How many independent power domains does the STM32MP131CAG3T require?

The STM32MP131CAG3T requires four independent regulated supplies: VDDCORE (1.0 V), VDDCPU (0.8–1.1 V), VDDIO (1.8–3.3 V), and VDDQ_DDR (1.2 V or 1.35 V). Each domain has dedicated power-on-reset and brown-out detection circuitry, and voltage monitors for VDDCORE, VDDCPU, and VDDQ_DDR are accessible via BSEC registers.

Can the STM32MP131CAG3T operate in extended temperature ranges?

Yes-the STM32MP131CAG3T is qualified for industrial temperature range (–40 °C to +105 °C ambient), with on-chip temperature sensors and thermal monitoring logic that triggers automatic throttling or system reset if junction temperature exceeds 125 °C. Thermal characteristics are documented in Section 7.4 of DS13877 Rev 7.