STMicroelectronics STM32MP131DAE7
- Part No.:
- STM32MP131DAE7
- Manufacturer:
- STMicroelectronics
- Category:
- Microprocessors
- Package:
- 289-LFBGA
- Datasheet:
-
STM32MP131DAE7.pdf
- Description:
- Linear IC's
- Quantity:
- Payment:

- Shipping:

Inventory:3,623
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
STM32MP131DAE7 from STMicroelectronics is a dual-core Arm® Cortex®-A7 microprocessor unit (MPU) operating up to 1 GHz, featuring integrated TrustZone® security, 1× Gigabit Ethernet MAC (IEEE 1588v2), 1× 12-bit ADC (5 Msps), and dual Quad-SPI interfaces - deployed in industrial HMI gateways requiring real-time Linux-based control with secure peripheral management.
For engineers reviewing the STM32MP131DAE7 datasheet, STM32MP131DAE7 pinout, STM32MP131DAE7 application, or STM32MP131DAE7 equivalent, key selection criteria include DDR3/LPDDR3 memory controller timing compliance, TrustZone-enabled peripheral isolation, Ethernet MAC RGMII/MII interface support, and LFBGA289 (14 × 14 mm, 0.8 mm pitch) mechanical compatibility.
Technical Context
The STM32MP131DAE7 implements a dual-bus interconnect architecture: a 64-bit AXI matrix running at up to 266 MHz for high-bandwidth CPU-to-DDR traffic, and a 32-bit AHB matrix at 209 MHz for peripheral access. It integrates four independent PLLs - including dedicated audio PLL for SAI/I2S clock accuracy and USB_PLL for high-speed PHY synchronization.
Security is enforced via hardware-enforced TrustZone address space controller (TZC) for DDR, embedded tamper detection (12 pins, 5 active), and BSEC-managed one-time programmable fuses (3072 bits, 96-bit UID). Power management includes five low-power modes (LPLV-Stop2, Standby with DDR retention) and on-chip LDOs for USB 1.8 V and core 1.1 V rails.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | Dual Arm® Cortex®-A7 @ up to 1 GHz - enables Linux-capable real-time processing with NEON™ acceleration for signal filtering. |
| Memory Interface | 16-bit DDR3/DDR3L-1066 or LPDDR2/LPDDR3-1066 controller - supports up to 1 Gbyte external SDRAM with hardware ECC for industrial reliability. |
| Security | Arm® TrustZone®, 12 tamper pins (5 active), ECDSA verification, SHA-256/512 HASH, true RNG (6 oscillators) - meets IEC 62443-3-3 SL2 requirements for secure boot and runtime attestation. |
| Connectivity | 1× Ethernet MAC/GMAC (MII/RMII/RGMII, IEEE 1588v2), 5× I2C FM+, 4× UART/USART, 5× SPI (50 Mbit/s), 2× SAI, SPDIF Rx - enables deterministic industrial networking and multi-sensor audio acquisition. |
| Analog Peripherals | 1× 12-bit ADC (5 Msps, internal VREF+), 1× temperature sensor, DFSDM (4-channel sigma-delta filter), digital VBAT monitoring - supports precision analog sensing without external signal conditioning. |
| Package | LFBGA289 (14 × 14 mm, 0.8 mm pitch, B0ED marking) - RoHS-compliant ECOPACK2 package with validated thermal resistance (θJA = 25.5 °C/W). |
| Power Supply | 1.71–3.6 V I/O supply (5 V-tolerant), on-chip 1.1 V LDO for CPU, 1.8 V LDO for USB PHY - simplifies power tree design by eliminating external regulators for critical rails. |
Pinout & Package
LFBGA289 (14 × 14 mm, 0.8 mm pitch, B0ED variant) with 289 solder balls arranged in 17 × 17 array; ball pitch and pad layout conform to JEDEC MO-275AC standard; thermal pad exposed on underside for PCB-level heat dissipation.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDDCORE | CPU core power supply | Supplies 1.1 V to Cortex-A7 cores; requires local 1 µF + 10 nF decoupling per power domain. |
| VDDIO_1 | I/O bank 1 supply | Configurable 1.71–3.6 V rail supporting 5 V-tolerant GPIOs; powers UART, I2C, and SPI peripherals. |
| ETH_MDIO / ETH_MDC | Ethernet management interface | Provides IEEE 802.3-compliant MDIO/MDC bus for PHY configuration and status readback. |
| RMII_REF_CLK | Ethernet reference clock input | Accepts 50 MHz single-ended clock for RMII mode; must meet ±50 ppm stability for IEEE 1588 timestamping. |
| BOOT0 | Boot mode selection | Pulled high during reset to enable boot from external Quad-SPI flash; level-sensitive, sampled at POR. |
| NRST | Asynchronous reset input | Active-low, Schmitt-triggered, internally pulled up; minimum pulse width 20 ns for reliable system reset. |
Key Features
| Feature | Design Value |
|---|---|
| TrustZone-enabled peripheral isolation | Hardware-enforced memory and peripheral access separation between secure/non-secure worlds - enables certified secure firmware updates and isolated crypto operations. |
| Dual-bus interconnect (AXI + AHB) | 64-bit AXI at 266 MHz handles DDR bandwidth; 32-bit AHB at 209 MHz routes peripheral DMA - eliminates CPU bottlenecks in multi-stream data acquisition. |
| Audio-class clocking | Dedicated audio PLL + 4× SAI + SPDIF RX with 4 inputs - supports simultaneous stereo I2S playback, PDM microphone capture, and professional audio sync over SPDIF. |
| Low-power retention modes | Standby mode retains DDR contents while drawing ≤15 µA; LPLV-Stop2 maintains RTC and backup SRAM at 1.8 µA - extends battery life in always-on edge nodes. |
| Flexible boot sources | Supports boot from Quad-SPI flash, SDMMC, eMMC, or USB OTG - enables field-upgradable firmware without JTAG dependency. |
Applications
| Industrial HMI Gateway | Secure Edge Node Controller |
|---|---|
Use Scenario: Programmable logic controller (PLC) edge gateway aggregating Modbus RTU sensors, OPC UA over Ethernet, and local web UI. IC Role / Device Role / Timing Role: Main application processor executing Yocto Linux, managing real-time EtherCAT slave stack, and synchronizing sensor timestamps via IEEE 1588v2 hardware. Use Value: Dual Cortex-A7 cores handle OS and deterministic control tasks concurrently; TrustZone isolates secure firmware update partition from user applications. |
Use Scenario: Battery-powered smart meter with tamper detection, encrypted metering data upload, and local display. IC Role / Device Role / Timing Role: Secure MPU managing AES-256 encryption, DFSDM-based current sensing, and RTC-corrected time-stamped logging. Use Value: On-chip tamper pins detect enclosure breach; backup SRAM retains logs during power loss; Standby mode enables >5-year battery life. |
| Audio Processing Terminal | IoT Gateway with Industrial Ethernet |
Use Scenario: Voice-controlled building automation panel with far-field microphone array and local speech inference. IC Role / Device Role / Timing Role: Audio subsystem host: SAI interfaces drive I2S codecs, DFSDM processes PDM mic streams, audio PLL ensures <100 ppm jitter for voice clarity. Use Value: Hardware-accelerated sigma-delta filtering offloads CPU; integrated temperature sensor compensates ADC gain drift across ambient range. |
Use Scenario: Field-deployed gateway connecting legacy RS-485 devices to cloud via TLS-secured MQTT over Ethernet. IC Role / Device Role / Timing Role: Network edge processor: Ethernet MAC handles TCP/IP stack, USB OTG enables field service firmware recovery, Quad-SPI hosts secure bootloader. Use Value: RGMII interface supports full-duplex 1 Gbps link; hardware CRC unit accelerates packet checksumming; 5 V-tolerant I/Os simplify RS-485 transceiver interfacing. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar MPU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| STM32MP157C-DK2 (MPU + Dev Board) | Quad-core Cortex-A7 @ 800 MHz, dual Cortex-M4 co-processor, 2× GbE, no integrated audio PLL | Targeted at higher-throughput multimedia gateways; lacks audio-class clocking and DFSDM | Select when needing dual-CPU heterogeneous compute (Linux + RTOS) and dual Ethernet, not audio fidelity. |
| i.MX 8M Mini (NXP) | Quad Cortex-A53 + Cortex-M4, 2× USB 3.0, MIPI-DSI, no TrustZone-peripheral isolation | Optimized for display-rich consumer IoT; weaker industrial security enforcement than STM32MP131's TZC+ETZPC | Choose for Android/Linux GUI applications where display interface matters more than tamper-hardened peripheral control. |
Compared with STM32MP131DAE7, the STM32MP157C offers higher CPU throughput but sacrifices audio-grade timing and compact LFBGA289 footprint; the i.MX 8M Mini delivers richer multimedia I/O yet lacks hardware-enforced peripheral trust zones required for certified industrial security.
Availability
STM32MP131DAE7 is available at Aetrix Electronics and suitable for industrial HMI gateways, secure edge node controllers, audio processing terminals, and IoT gateways requiring stable component supply across extended product lifecycles.
Supply support for STM32MP131DAE7 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power ICs, sensors, and automotive semiconductors since 1987.
The STM32MP series targets Linux-capable industrial and edge computing applications, combining Arm application processors with real-time MCU-like peripherals and hardware security - bridging the gap between microprocessors and microcontrollers.
FAQ
What is the maximum DDR memory capacity supported by STM32MP131DAE7?
The STM32MP131DAE7 supports up to 1 Gbyte of external DDR memory via its 16-bit DDR3/DDR3L-1066 or LPDDR2/LPDDR3-1066 controller. This includes hardware support for 8-bit ECC on SLC NAND and configurable burst lengths aligned to JEDEC standards for industrial-grade reliability.
Does STM32MP131DAE7 include hardware cryptographic acceleration?
Yes - it integrates a dedicated HASH processor supporting SHA-1, SHA-224/256/384/512, and SHA-3, plus HMAC; a public key accelerator (PKA) for ECDSA verification; and a true random number generator with six triple oscillators meeting NIST SP 800-90B entropy requirements.
What debug interfaces are available on STM32MP131DAE7?
The device provides Arm® CoreSight™ trace and debug via SWD and JTAG interfaces, both usable as general-purpose GPIOs when not in debug mode. It includes a 4-Kbyte embedded trace buffer and supports secure debug authentication through TrustZone-protected debug registers.
Can STM32MP131DAE7 operate in battery-backed standby mode?
Yes - it supports VBAT operation with dedicated backup regulator (~0.9 V), enabling RTC, backup SRAM (8 Kbytes), and tamper detection to remain active during main power loss. Standby mode draws ≤15 µA while retaining full DDR contents for instant resume.
STM32MP131DAE7 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Package/Case:
- 289-LFBGA
- Series:
- STM32MP1
- Packaging:
- Tray
- Product Status:
- Active
- Core Processor:
- ARM® Cortex®-A7
- Number of Cores/Bus Width:
- 1 Core, 32-Bit
- Speed:
- 1GHz
- Co-Processors/DSP:
- Multimedia; NEON™ SIMD
- RAM Controllers:
- DDR3, DDR3L, LPDDR2, LPDDR3
- Graphics Acceleration:
- Yes
- Display & Interface Controllers:
- LCD
- Ethernet:
- 10/100/1000Mbps (1)
- SATA:
- -
- USB:
- USB 2.0 (2)
- Voltage - I/O:
- 1.8V, 2.5V, 3.3V
- Operating Temperature:
- -40°C ~ 105°C (TJ)
- Grade:
- -
- Qualification:
- -
- Security Features:
- AES, ARM TZ, Boot Security, Cryptography, Secure Debug, SHA-1/2, Tamper Detection, TRNG, Volatile key Storage
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 289-LFBGA (14x14)
- Additional Interfaces:
- GPIO, I2C, I2S, IrDA, MMC/SD/SDIO, SAI, SPDIF, SPI, UART/USART, USB
STM32MP131DAE7 FAQ
1.How can I place an order for STM32MP131DAE7 through Aetrix?
Please submit a Request for Quotation (RFQ) for STM32MP131DAE7 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for STM32MP131DAE7 reliable?
The price and inventory of STM32MP131DAE7 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for STM32MP131DAE7 is usually 5 days.
3.What payment methods are accepted for STM32MP131DAE7?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for STM32MP131DAE7 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for STM32MP131DAE7?
STM32MP131DAE7 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your STM32MP131DAE7 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for STM32MP131DAE7?
For technical support, including STM32MP131DAE7 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your STM32MP131DAE7 requirements.
6.How does Aetrix verify that STM32MP131DAE7 is sourced from the original manufacturer or authorized distributors?
All STM32MP131DAE7 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that STM32MP131DAE7 meets industry standards.
7.What is the process for return or replacement of STM32MP131DAE7?
All STM32MP131DAE7 units undergo pre-shipment inspection (PSI). If there is an issue with STM32MP131DAE7, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The STM32MP131DAE7 part is unused and in its original packaging.
Return procedure for STM32MP131DAE7:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
STM32MP131DAE7 Tags

-
AT91SAM9260B-CU-999
Microchip Technology

-
AT91SAM9G25-CU
Microchip Technology

-
ATSAMA5D27C-CU
Microchip Technology

-
AT91SAM9X35-CU
Microchip Technology

-
AT91SAM9X25-CU
Microchip Technology

-
MCIMX6Y2CVM08AB
NXP Semiconductors
-
AM3352BZCZ100
Texas Instruments

-
AT91SAM9260B-CU
Microchip Technology

-
AT91SAM9260B-QU
Microchip Technology

-
ATSAMA5D31A-CU
Microchip Technology

-
AT91SAM9G20B-CU-999
Microchip Technology

-
MCIMX6Y2CVM05AB
NXP Semiconductors
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

