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STMicroelectronics STM32MP133AAE3

Part No.:
STM32MP133AAE3
Manufacturer:
STMicroelectronics
Category:
Microprocessors
Package:
289-LFBGA
Datasheet:
AetrixSTM32MP133AAE3.pdf
Description:
Linear IC's
Quantity:
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Inventory:2,300

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Product details

Overview

STM32MP133AAE3 from STMicroelectronics is a dual-core Arm® Cortex®-A7 microprocessor operating up to 1 GHz, featuring dual 10/100/1000 Mbps Ethernet MACs, dual CAN FD controllers, two 12-bit ADCs (5 Msps), and hardware TrustZone® security. It integrates 128 KB L2 cache, 168 KB on-chip SRAM (including 8 KB in backup domain), and supports LPDDR2/LPDDR3-1066 and DDR3/DDR3L-1066 external memory-designed for industrial HMI, edge gateway, and secure IoT gateway applications.

For engineers reviewing the STM32MP133AAE3 datasheet, STM32MP133AAE3 pinout, STM32MP133AAE3 application, or STM32MP133AAE3 equivalent, key selection considerations include dual Ethernet + CAN FD coexistence, DDR retention in Standby mode, TrustZone-enabled peripheral isolation, and 135 secure GPIOs with tamper detection capability.

Technical Context

The STM32MP133AAE3 implements a heterogeneous dual-core Arm Cortex-A7 subsystem with NEON and TrustZone extensions, backed by 128 KB unified L2 cache and independent AXI/AHB interconnect matrices (266 MHz / 209 MHz). Its memory subsystem includes dedicated DDR controller supporting 16-bit LPDDR2/LPDDR3-1066 and DDR3/DDR3L-1066, plus TZC-based address space protection for secure memory partitioning.

Security architecture integrates ETZPC for peripheral trust assignment, BSEC for OTP control, PKA for ECDSA verification, HASH engine (SHA-256/SHA-384/SHA-512), and 3-oscillator TRNG. Clock management employs four fractional PLLs-including USB_PLL and audio PLL-for precise timing across high-speed interfaces (USB HS, SAI, SPDIF) and real-time peripherals (RTC, timers, watchdogs).

Key Specifications

ParameterValue and Actual Design Meaning
CPU CoreDual Arm Cortex-A7 @ up to 1 GHz with NEON, TrustZone, 32 KB I-cache/32 KB D-cache, 128 KB L2 cache
Memory Interface16-bit DDR3/DDR3L-1066 or LPDDR2/LPDDR3-1066 support up to 1 Gbyte; 168 KB on-chip SRAM (128 KB AXI SYSRAM + 32 KB AHB SRAM + 8 KB Backup SRAM)
Connectivity2× IEEE 1588v2-capable Ethernet MAC/GMAC (MII/RMII/RGMII); 2× CAN FD controllers; 2× USB 2.0 HS Host or 1× Host + 1× OTG
Analog Peripherals2× 12-bit ADCs (5 Msps max); 1× temperature sensor; 1× DFSDM (4-channel sigma-delta filter); internal VREF+ reference buffer
Security FeaturesTrustZone-enabled peripherals; 12× tamper pins (5 active); ECDSA/PKA acceleration; SHA-256/384/512 & HMAC; 3-oscillator TRNG; 3072-bit fuses (96-bit UID)
Power ManagementSupports Sleep, Stop, LPLV-Stop, LPLV-Stop2, Standby modes; DDR retention in Standby; on-chip LDOs (1.8 V USB, 1.1 V core); backup regulator (~0.9 V)
PackageTFBGA289 (9 × 9 mm, 0.5 mm pitch), ECOPACK2-compliant, ball count 289

Pinout & Package

STM32MP133AAE3 is housed in a TFBGA289 package (9 × 9 mm, 0.5 mm pitch), compliant with ECOPACK2 environmental standards. Pin definitions follow ST's documented ball map (DS13876 Rev 7, Table 7), with dedicated power domains (VDDCORE, VDDCPU, VDDIO, VDDQ_DDR), multiple supply/ground pairs for noise immunity, and configurable I/O banks supporting 5 V-tolerant operation.

Pin/TerminalCircuit RoleDesign Meaning
VDDCORECore power supply1.1 V nominal supply for Cortex-A7 cores and L2 cache; requires low-noise decoupling
VDDCPUCPU voltage rail1.1 V supply specifically for CPU subsystem; monitored via internal sensor
VDDIOI/O power domain1.71–3.6 V programmable I/O supply; enables 5 V-tolerant operation on selected pins
VDDQ_DDRDDR I/O voltage1.2 V or 1.35 V supply for DDR interface; supports LPDDR2/LPDDR3 and DDR3/DDR3L signaling
NRSTActive-low reset inputAsynchronous reset pin with Schmitt trigger; initiates full system reset including debug and security blocks
BOOT0Boot mode selectionConfigures primary boot source (eMMC, SD, SPI NOR, Quad-SPI, NAND) at power-up
ETH1_RXD0–3Ethernet receive dataDedicated RGMII/MII inputs for first Gigabit Ethernet interface; routed to internal MAC with IEEE 1588v2 timestamping
FDCAN1_TX/RXCAN FD transceiver interfaceDifferential pair for first CAN FD controller; supports bit rates up to 5 Mbps with protocol-level FD framing

Key Features

FeatureDesign Value
Dual Cortex-A7 with TrustZoneEnables secure world/non-secure world software separation for certified RTOS and Linux kernel isolation
DDR retention in StandbyMaintains full DDR content during ultra-low-power Standby mode-critical for fast wake-up in edge gateways
Hardware-accelerated cryptoSHA-256/384/512, HMAC, ECDSA verification, and TRNG eliminate host CPU overhead for TLS and firmware signing
24 timers + 2 watchdogsIncludes 2× 32-bit general-purpose timers with quadrature encoder input, 5× low-power timers, and secure RTC with sub-second accuracy
Flexible memory interfaceDual Quad-SPI + FMC supporting SLC NAND (8-bit ECC) and parallel NOR/NAND-enables boot-from-NAND and firmware update resilience

Applications

Industrial HMIEdge Gateway

Use Scenario: Touch-enabled panel PC controlling PLCs and sensors in factory automation.

IC Role / Device Role / Timing Role: Main application processor running Linux with Qt-based GUI, managing real-time EtherCAT over Ethernet and fieldbus bridging via CAN FD.

Use Value: Dual Ethernet + dual CAN FD enables concurrent industrial network protocols; DDR retention ensures <100 ms UI resume from Standby after power interruption.

Use Scenario: Smart building gateway aggregating BACnet/IP, Modbus TCP, and KNX traffic across wired/wireless networks.

IC Role / Device Role / Timing Role: Secure edge compute node executing protocol translation, local policy enforcement, and OTA firmware validation using TrustZone-protected PKA and HASH engines.

Use Value: Hardware crypto acceleration reduces TLS handshake latency by >60% vs. software-only; tamper pins detect physical intrusion attempts on enclosure.

Secure IoT GatewayAudio-Enabled Edge Node

Use Scenario: Cellular-connected gateway for remote asset monitoring with encrypted sensor telemetry and secure cloud onboarding.

IC Role / Device Role / Timing Role: Root-of-trust anchor with secure boot, measured boot, and runtime attestation-leveraging BSEC fuses and TrustZone-peripheral isolation.

Use Value: 96-bit unique ID and 1280-bit user-programmable fuses enable device identity binding and lifecycle key provisioning without external SE.

Use Scenario: Voice-controlled smart speaker with local wake-word detection and multi-mic beamforming.

IC Role / Device Role / Timing Role: Audio subsystem controller interfacing PDM mics via DFSDM, driving stereo speakers via SAI/I2S, and synchronizing SPDIF RX inputs.

Use Value: Dual SAI + SPDIF RX + audio PLL deliver <1 ppm jitter for professional-grade audio playback; DFSDM filters raw PDM streams at 1 MSPS per channel.

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-core application processor applications.

Alternative PartTechnical DifferenceApplication DifferenceSelection Advice
STM32MP157C-DK2 (eval board)Same MP1 family, but MP157C uses Cortex-A7 @ 800 MHz, lacks CAN FD, has single Ethernet MAC, and no SPDIF RXSuitable for cost-sensitive HMI without industrial fieldbus requirementsSelect when CAN FD and dual Ethernet are not required; lower BOM cost but reduced real-time I/O flexibility
i.MX 8M Mini (NXP)Quad-core Cortex-A53 @ 1.8 GHz, no TrustZone-peripheral isolation, different security model (CAAM vs. PKA/HASH), no integrated tamper pinsBetter for multimedia-rich UIs; weaker for certified secure boot and physical tamper responseChoose for Android/Linux multimedia stacks; avoid where ST-specific TrustZone peripheral control or tamper detection is mandated

Compared with STM32MP133AAE3, the MP157C offers lower performance and fewer industrial interfaces but simpler licensing; the i.MX 8M Mini delivers higher CPU throughput and GPU support but requires external secure elements for comparable tamper resilience and lacks native SPDIF RX for pro-audio integration.

Availability

STM32MP133AAE3 is available at Aetrix Electronics and suitable for industrial HMI, edge gateway, and secure IoT gateway applications requiring stable component supply, long-term lifecycle assurance, and qualified automotive/industrial temperature grade support.

Supply support for STM32MP133AAE3 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, specializing in microcontrollers, power management, analog ICs, and MEMS sensors-with over 40 years of industrial and automotive qualification expertise.

The STM32MP series targets heterogeneous multicore applications demanding Linux-capable processing, real-time responsiveness, and hardware-enforced security-designed specifically for industrial edge, smart infrastructure, and trusted IoT endpoints.

FAQ

What is the maximum supported DDR memory capacity and type for STM32MP133AAE3?

The STM32MP133AAE3 supports up to 1 Gbyte of external DDR memory, compatible with LPDDR2/LPDDR3-1066 (16-bit bus) and DDR3/DDR3L-1066 (16-bit bus). The DDR controller includes 8-bit ECC support for SLC NAND and robust signal integrity features like write leveling and read leveling calibration.

Does STM32MP133AAE3 support secure boot and runtime attestation?

Yes-secure boot is enforced via BSEC OTP fuses and TrustZone-assisted ROM code that verifies signed bootloader images. Runtime attestation is enabled through hardware-accelerated ECDSA signature verification, SHA-256/384 hashing, and secure RTC-backed timestamping-meeting requirements for PSA Certified Level 2 and IEC 62443-3-3 compliance.

How many I/O pins support 5 V tolerance, and what configuration is required?

Up to 135 GPIOs are 5 V-tolerant when VDDIO is supplied within 1.71–3.6 V and the corresponding GPIOx_MODER bits are set to input or output mode (not analog). No external level shifters are needed for interfacing with legacy 5 V logic, simplifying design of mixed-voltage industrial control boards.

What debugging interfaces does STM32MP133AAE3 provide, and are they usable as GPIOs?

The device integrates Arm CoreSight™ debug infrastructure with SWD and JTAG interfaces, both of which can be remapped as general-purpose GPIOs after debug initialization. A 4-Kbyte embedded trace buffer supports real-time instruction tracing, and debug pins retain full functionality even when configured as GPIOs in non-debug operation.

STM32MP133AAE3 Specifications

Product attributes
Attribute value
Manufacturer:
STMicroelectronics
Package/Case:
289-LFBGA
Series:
STM32MP1
Packaging:
Tray
Product Status:
Active
Core Processor:
ARM® Cortex®-A7
Number of Cores/Bus Width:
1 Core, 32-Bit
Speed:
650MHz
Co-Processors/DSP:
Multimedia; NEON™ SIMD
RAM Controllers:
DDR3, DDR3L, LPDDR2, LPDDR3
Graphics Acceleration:
Yes
Display & Interface Controllers:
LCD
Ethernet:
10/100/1000Mbps (2)
SATA:
-
USB:
USB 2.0 (2)
Voltage - I/O:
1.8V, 2.5V, 3.3V
Operating Temperature:
-40°C ~ 125°C (TJ)
Grade:
-
Qualification:
-
Security Features:
AES, ARM TZ, Boot Security, Cryptography, Secure Debug, SHA-1/2, Tamper Detection, TRNG, Volatile key Storage
Mounting Type:
Surface Mount
Supplier Device Package:
289-LFBGA (14x14)
Additional Interfaces:
CANbus, GPIO, I2C, I2S, IrDA, MMC/SD/SDIO, SAI, SPDIF, SPI, UART/USART

STM32MP133AAE3 FAQ

1.How can I place an order for STM32MP133AAE3 through Aetrix?

Please submit a Request for Quotation (RFQ) for STM32MP133AAE3 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for STM32MP133AAE3 reliable?

The price and inventory of STM32MP133AAE3 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for STM32MP133AAE3 is usually 5 days.

3.What payment methods are accepted for STM32MP133AAE3?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for STM32MP133AAE3 transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for STM32MP133AAE3?

STM32MP133AAE3 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your STM32MP133AAE3 order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for STM32MP133AAE3?

For technical support, including STM32MP133AAE3 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your STM32MP133AAE3 requirements.

6.How does Aetrix verify that STM32MP133AAE3 is sourced from the original manufacturer or authorized distributors?

All STM32MP133AAE3 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that STM32MP133AAE3 meets industry standards.

7.What is the process for return or replacement of STM32MP133AAE3?

All STM32MP133AAE3 units undergo pre-shipment inspection (PSI). If there is an issue with STM32MP133AAE3, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The STM32MP133AAE3 part is unused and in its original packaging.

Return procedure for STM32MP133AAE3:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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