STMicroelectronics STM32MP133AAG3
- Part No.:
- STM32MP133AAG3
- Manufacturer:
- STMicroelectronics
- Category:
- Microprocessors
- Package:
- 289-TFBGA
- Datasheet:
-
STM32MP133AAG3.pdf
- Description:
- Linear IC's
- Quantity:
- Payment:

- Shipping:

Inventory:3,341
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
STM32MP133AAG3 from STMicroelectronics is a dual-core Arm® Cortex®-A7 microprocessor operating up to 1 GHz, featuring dual Ethernet MAC/GMAC (IEEE 1588v2), dual CAN FD controllers, two 12-bit ADCs (5 Msps), and TrustZone® security. It integrates 128 KB L2 cache, 168 KB on-chip SRAM (AXI/AHB/Backup domains), and supports LPDDR2/LPDDR3-1066 or DDR3/DDR3L-1066 external memory - deployed in industrial HMI, edge gateway, and secure IoT gateway applications.
For engineers reviewing the STM32MP133AAG3 datasheet, STM32MP133AAG3 pinout, STM32MP133AAG3 application, or STM32MP133AAG3 equivalent, key selection considerations include dual-CAN FD timing synchronization, IEEE 1588v2 hardware timestamping for deterministic networking, TrustZone-enabled peripheral isolation, and 135-pin secure GPIO count with wakeup capability.
Technical Context
The STM32MP133AAG3 implements a dual-core Arm Cortex-A7 subsystem with NEON and TrustZone, backed by 128 KB unified L2 cache and independent L1 I/D caches (32 KB each). Its interconnect comprises a 64-bit AXI matrix (266 MHz) and 32-bit AHB matrix (209 MHz), enabling concurrent high-bandwidth access to DDR, peripherals, and DMA channels.
Security architecture includes TrustZone address space controller (TZC) for DDR, embedded TrustZone protection controller (ETZPC), 12 tamper pins (5 active), BSEC OTP with 3072-bit fuses, and hardware accelerators for HASH (SHA-256/512), ECDSA verification, RNG (6 triple oscillators), and DFSDM (4-channel sigma-delta filtering).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | Dual Arm Cortex-A7 @ up to 1 GHz with NEON, TrustZone, 128 KB L2 cache |
| Memory Interface | LPDDR2/LPDDR3-1066 or DDR3/DDR3L-1066 (16-bit bus, up to 1 Gbyte) |
| On-chip SRAM | 168 KB total: 128 KB AXI SYSRAM + 32 KB AHB SRAM + 8 KB Backup domain SRAM |
| Connectivity | 2× Ethernet MAC/GMAC (MII/RMII/RGMII, IEEE 1588v2), 2× CAN FD, 5× I2C, 8× UART/USART, 5× SPI, 2× SAI, SPDIF Rx (4 inputs) |
| Analog Peripherals | 2× 12-bit ADCs (5 Msps), 1× temperature sensor, 1× DFSDM (4 channels, 2 filters), VREFBUF |
| Security | TrustZone peripherals, 12× tamper pins (5 active), BSEC OTP, HASH (SHA-256/512), ECDSA, RNG, CRC unit |
| Power Management | 1.71–3.6 V I/O supply (5 V-tolerant), POR/PDR/PVD/BOR, LDOs (1.8 V USB, 1.1 V core), DDR retention in Standby |
Pinout & Package
STM32MP133AAG3 is packaged in TFBGA289 (9 × 9 mm, 0.5 mm pitch), compliant with ECOPACK2 environmental standards. Pin definitions are validated per STMicroelectronics DS13876 Rev 7 Section 4 (Pinout, pin description and alternate functions) and Table 7 (ball definitions).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD | Core power supply | 1.1 V nominal supply for CPU and logic domains; requires local decoupling per datasheet layout guidelines |
| VDDIO | I/O power supply | 1.71–3.6 V supply enabling 5 V-tolerant operation; configurable per bank for mixed-voltage interfaces |
| NRST | Active-low reset input | Asynchronous reset signal with internal pull-up; initiates full system reset including Cortex-A7 and peripherals |
| BOOT0 | Boot mode selection | Configures primary boot source (eMMC, SD, NAND, QSPI, USB) at power-on; sampled during reset sequence |
| ETH1_RXD0–3 / ETH1_TXD0–3 | Ethernet physical layer interface | Dedicated RMII/RGMII signals for first Gigabit Ethernet MAC; supports IEEE 1588v2 hardware timestamping |
| FDCAN1_TX / FDCAN1_RX | CAN FD transceiver interface | Differential pair supporting CAN FD protocol up to 5 Mbit/s; integrated TX delay compensation and bit timing registers |
Key Features
| Feature | Design Value |
|---|---|
| Dual Cortex-A7 with L2 cache | Enables asymmetric multiprocessing (AMP) or symmetric multiprocessing (SMP) Linux deployment with deterministic real-time response via dedicated timer subsystem |
| IEEE 1588v2 hardware support | Provides sub-100 ns timestamp accuracy on both Ethernet MACs for time-sensitive networking (TSN) in industrial automation |
| TrustZone-enabled peripheral isolation | Allows secure firmware execution and isolated peripheral access (e.g., crypto engines, tamper sensors) without software overhead |
| DFSDM with 4-channel sigma-delta input | Supports direct connection to MEMS microphones or pressure sensors without external ADC, reducing BOM and PCB area |
| Low-power modes with DDR retention | Standby mode maintains full DDR content while consuming <100 µA, enabling instant resume for edge AI inference workloads |
Applications
| Industrial HMI | Secure Edge Gateway |
|---|---|
Use Scenario: Touch-enabled factory floor display with real-time machine status, alarm logging, and remote diagnostics over cellular backhaul. IC Role / Device Role / Timing Role: Main application processor executing Linux-based Qt UI, managing dual Ethernet for PLC communication and CAN FD for fieldbus integration, with hardware-accelerated SHA-256 for OTA firmware signature verification. Use Value: Dual 12-bit ADCs monitor analog sensor inputs (temperature, vibration); TrustZone isolates secure boot and credential storage from UI runtime. | Use Scenario: Smart building controller aggregating BACnet MS/TP, Modbus RTU, and KNX devices into a unified IP network with TLS-secured cloud telemetry. IC Role / Device Role / Timing Role: Central protocol translator and security anchor - runs dual CAN FD for legacy fieldbus bridging, dual Ethernet for redundant LAN uplinks, and hardware RNG for TLS session key generation. Use Value: DFSDM processes audio alerts from occupancy sensors; SPDIF Rx handles digital audio streams for voice feedback; LPLV-Stop2 mode enables <5 µA sleep current during idle periods. |
| Automotive Diagnostic Tool | Medical Data Logger |
Use Scenario: Handheld OBD-II scanner supporting UDS over CAN FD, DoIP over Ethernet, and wireless firmware updates via USB OTG. IC Role / Device Role / Timing Role: High-speed protocol engine - uses FDCAN2 for vehicle ECU diagnostics, ETH2 for DoIP routing, and USB OTG for secure update delivery with BSEC-locked firmware validation. Use Value: 135 secure GPIOs enable custom JTAG/SWD debug port remapping; CRC unit validates flash integrity before boot; tamper pins detect physical intrusion attempts. | Use Scenario: Portable patient monitor recording ECG, SpO₂, and respiration waveforms with encrypted local storage and HIPAA-compliant cloud sync. IC Role / Device Role / Timing Role: Real-time data acquisition hub - ADC1 samples ECG at 5 Msps with oversampling, SAI1 streams PDM microphone data, and TrustZone enforces strict separation between clinical data path and Wi-Fi stack. Use Value: Temperature sensor and VREFBUF ensure ADC accuracy across ambient range; backup domain SRAM retains RTC calendar and last vital sign snapshot during battery swap. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-core Arm Cortex-A7 microprocessor applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| STM32MP157CAB3 | Single Cortex-A7 core (up to 800 MHz), no DFSDM, lower GPIO count (128), lacks SPDIF Rx | Suitable for cost-sensitive HMI with basic connectivity; insufficient for multi-sensor audio/data fusion | Select when dual-core SMP is unnecessary and SPDIF/DFSDM are unused - reduces BOM cost by ~18% |
| i.MX 8M Mini (LPC55S69) | Quad Cortex-A53 + Cortex-M33, higher compute throughput but larger thermal envelope; no native CAN FD, requires external transceiver | Better for multimedia-rich UIs or ML inference; less optimal for CAN FD–centric industrial control | Choose for Android/Linux GUI performance headroom; avoid if CAN FD timing determinism and compact TFBGA289 footprint are critical |
Compared with STM32MP133AAG3, STM32MP157CAB3 trades dual-core capability and audio peripherals for lower cost and power, while i.MX 8M Mini offers higher CPU performance at the expense of CAN FD integration, package size, and real-time peripheral latency.
Availability
STM32MP133AAG3 is available at Aetrix Electronics and suitable for industrial HMI, secure edge gateways, and automotive diagnostic tools requiring stable component supply, long lifecycle assurance, and qualified automotive-grade traceability.
Supply support for STM32MP133AAG3 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, specializing in microcontrollers, power management, sensors, and automotive ICs with ISO 9001 and IATF 16949 certification.
The STM32MP series targets heterogeneous computing for industrial and IoT edge devices, combining Cortex-A application processing with Cortex-M real-time control and hardware security - designed specifically for Linux-capable, safety-aware, and resource-constrained embedded systems.
FAQ
What boot sources does STM32MP133AAG3 support?
STM32MP133AAG3 supports boot from eMMC, SD card, SLC NAND, Quad-SPI NOR flash, and USB device via BOOT0 pin configuration. The BSEC block enforces secure boot chain using SHA-256 hash verification of first-stage bootloader (FSBL) stored in internal ROM or external memory.
Does STM32MP133AAG3 include hardware cryptographic acceleration?
Yes - it integrates dedicated hardware accelerators for HASH (SHA-1/224/256/384/512, SHA-3), HMAC, ECDSA signature verification, true random number generation (6 triple oscillators), and CRC calculation. These operate independently of the Cortex-A7 cores to offload security-critical operations.
How many low-power modes are available and what is the lowest current draw?
Five low-power modes are supported: Sleep, Stop, LPLV-Stop, LPLV-Stop2, and Standby. In LPLV-Stop2 mode, typical current draw is 5 µA with RTC and backup SRAM active; Standby mode achieves <100 µA with DDR retention enabled - verified per DS13876 Rev 7 Section 6.3.7.
Is STM32MP133AAG3 pin-compatible with other STM32MP13x variants?
Yes - all STM32MP13x devices (A/D suffixes) share identical TFBGA289 and LFBGA289 packages and pinout. Differences are limited to internal feature sets (e.g., STM32MP133A includes both CAN FD controllers; STM32MP131A omits one), not physical connectivity or power delivery requirements.
STM32MP133AAG3 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Package/Case:
- 289-TFBGA
- Series:
- STM32MP1
- Packaging:
- Tray
- Product Status:
- Active
- Core Processor:
- ARM® Cortex®-A7
- Number of Cores/Bus Width:
- 1 Core, 32-Bit
- Speed:
- 650MHz
- Co-Processors/DSP:
- Multimedia; NEON™ SIMD
- RAM Controllers:
- DDR3, DDR3L, LPDDR2, LPDDR3
- Graphics Acceleration:
- Yes
- Display & Interface Controllers:
- LCD
- Ethernet:
- 10/100/1000Mbps (2)
- SATA:
- -
- USB:
- USB 2.0 (2)
- Voltage - I/O:
- 1.8V, 2.5V, 3.3V
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Security Features:
- AES, ARM TZ, Boot Security, Cryptography, Secure Debug, SHA-1/2, Tamper Detection, TRNG, Volatile key Storage
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 289-TFBGA (9x9)
- Additional Interfaces:
- CANbus, GPIO, I2C, I2S, IrDA, MMC/SD/SDIO, SAI, SPDIF, SPI, UART/USART
STM32MP133AAG3 FAQ
1.How can I place an order for STM32MP133AAG3 through Aetrix?
Please submit a Request for Quotation (RFQ) for STM32MP133AAG3 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for STM32MP133AAG3 reliable?
The price and inventory of STM32MP133AAG3 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for STM32MP133AAG3 is usually 5 days.
3.What payment methods are accepted for STM32MP133AAG3?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for STM32MP133AAG3 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for STM32MP133AAG3?
STM32MP133AAG3 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your STM32MP133AAG3 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for STM32MP133AAG3?
For technical support, including STM32MP133AAG3 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your STM32MP133AAG3 requirements.
6.How does Aetrix verify that STM32MP133AAG3 is sourced from the original manufacturer or authorized distributors?
All STM32MP133AAG3 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that STM32MP133AAG3 meets industry standards.
7.What is the process for return or replacement of STM32MP133AAG3?
All STM32MP133AAG3 units undergo pre-shipment inspection (PSI). If there is an issue with STM32MP133AAG3, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The STM32MP133AAG3 part is unused and in its original packaging.
Return procedure for STM32MP133AAG3:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
STM32MP133AAG3 Tags

-
AT91SAM9260B-CU-999
Microchip Technology

-
AT91SAM9G25-CU
Microchip Technology

-
ATSAMA5D27C-CU
Microchip Technology

-
AT91SAM9X35-CU
Microchip Technology

-
AT91SAM9X25-CU
Microchip Technology

-
MCIMX6Y2CVM08AB
NXP Semiconductors
-
AM3352BZCZ100
Texas Instruments

-
AT91SAM9260B-CU
Microchip Technology

-
AT91SAM9260B-QU
Microchip Technology

-
ATSAMA5D31A-CU
Microchip Technology

-
AT91SAM9G20B-CU-999
Microchip Technology

-
MCIMX6Y2CVM05AB
NXP Semiconductors
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

