STMicroelectronics STM32MP133CAE3

Overview

STM32MP133CAE3 from STMicroelectronics is a dual-core Arm® Cortex®-A7 microprocessor unit (MPU) operating up to 1 GHz, featuring dual Ethernet MAC/GMAC (IEEE 1588v2), dual CAN FD controllers, dual 12-bit ADCs (5 Msps), hardware crypto acceleration (AES-128/192/256, SHA-256/384/512, PKA), and TrustZone®-enabled secure boot. It targets industrial HMI, edge gateway, and smart building control systems requiring real-time connectivity and cryptographic integrity.

For engineers reviewing the STM32MP133CAE3 datasheet, STM32MP133CAE3 pinout, STM32MP133CAE3 application, or STM32MP133CAE3 equivalent, key selection considerations include DDR3/LPDDR3 memory interface support, 2×CAN FD + 2×Ethernet timing coexistence, TrustZone-secured peripheral isolation, and LFBGA289 (14 × 14 mm, 0.8 mm pitch) mechanical compatibility with industrial PCB layouts.

Technical Context

The STM32MP133CAE3 implements a heterogeneous dual-core Arm Cortex-A7 subsystem with 128 KB unified L2 cache, NEON™ SIMD support, and TrustZone® for hardware-enforced secure/non-secure world separation. Its interconnect comprises a 64-bit AXI bus matrix (266 MHz) and 32-bit AHB matrix (209 MHz), enabling concurrent high-bandwidth DDR access and low-latency peripheral control.

Security is architected via BSEC OTP fuses (3072-bit, including 96-bit UID and 256-bit HUK), tamper detection (12 pins, 5 active), and dedicated crypto accelerators - AES on-the-fly DRAM encryption, HASH (SHA-1/2/3), PKA (ECC/RSA), and TRNG (6 triple oscillators). Power management includes five low-power modes with DDR retention in Standby and integrated LDOs (1.1 V, 1.8 V, ~0.9 V backup).

Key Specifications

Pinout & Package

LFBGA289 package (B0ED variant), 14 × 14 mm body, 0.8 mm ball pitch, 289 I/O balls arranged in 17 × 17 array with corner balls omitted. Compatible with standard reflow profiles and industrial-grade thermal cycling requirements.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-core Arm A-class MPU applications.

Compared with STM32MP133CAE3, the STM32MP157C offers higher display bandwidth but sacrifices CAN FD and on-the-fly DRAM encryption; the i.MX 8M Mini delivers greater CPU throughput but lacks fine-grained TrustZone peripheral protection and tamper-hardened boot.

Availability

STM32MP133CAE3 is available at Aetrix Electronics and suitable for industrial HMI, smart building edge controllers, and secure gateways requiring stable component supply, long-term lifecycle assurance, and ECOPACK2-compliant packaging.

Supply support for STM32MP133CAE3 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power ICs, sensors, and automotive semiconductors since 1987.

The STM32MP series targets heterogeneous computing for industrial and IoT edge devices, combining real-time Linux-capable application cores with microcontroller-like peripheral integration and hardware security.

FAQ

What boot sources does the STM32MP133CAE3 support?

The STM32MP133CAE3 supports boot from eMMC, SD card, NAND flash, Quad-SPI NOR flash, and USB mass storage via configurable BOOT pins and internal ROM loader. Boot mode is latched at reset and validated by secure boot firmware before loading FSBL from selected medium.

Does the STM32MP133CAE3 include hardware debug support?

Yes - it integrates Arm CoreSight™ debug infrastructure with SWD and JTAG interfaces, both usable as GPIOs when debug is disabled. A 4-Kbyte embedded trace buffer enables instruction-level tracing, and debug access is gated by TrustZone security state.

How is DDR memory retention managed in low-power modes?

In Standby mode, the STM32MP133CAE3 maintains DDR SDRAM contents using self-refresh while powering down CPU cores, caches, and most peripherals. The DDR controller retains configuration, and wakeup restores full operation within microseconds without memory reload.

What is the maximum resolution and sampling rate of its ADCs?

The STM32MP133CAE3 integrates two independent 12-bit SAR ADCs, each capable of up to 5 Msps (mega-samples per second) with programmable sampling time and hardware oversampling. Both support external VREF+ and operate across the full industrial temperature range (−40°C to +125°C).