STMicroelectronics STM32MP133CAG3

Overview

STM32MP133CAG3 from STMicroelectronics is a dual-core Arm® Cortex®-A7 microprocessor operating up to 1 GHz, featuring dual Ethernet MAC/GMAC (IEEE 1588v2), dual CAN FD controllers, two 12-bit ADCs (5 Msps), hardware crypto acceleration (AES-128/192/256, SHA-256/512, PKA), and TrustZone®-enabled secure boot. It targets industrial HMI, edge gateway, and smart building control systems requiring real-time connectivity and cryptographic integrity.

For engineers reviewing the STM32MP133CAG3 datasheet, STM32MP133CAG3 pinout, STM32MP133CAG3 application, or STM32MP133CAG3 equivalent, key selection considerations include DDR3/LPDDR3 memory interface timing, CAN FD bit-rate configurability, TrustZone peripheral partitioning, and dual-USB HS host/OTG coexistence capability.

Technical Context

The STM32MP133CAG3 integrates two Arm Cortex-A7 cores with shared 128 KB L2 cache, NEON™ SIMD support, and TrustZone® for hardware-enforced secure/non-secure world isolation. Its interconnect matrix comprises a 64-bit AXI bus (266 MHz) and 32-bit AHB bus (209 MHz), enabling concurrent high-bandwidth peripheral access.

Security architecture includes BSEC OTP fuses (3072-bit), tamper detection on 12 pins (5 active), AES-256 DRAM encryption, and dedicated PKA for ECC/RSA with DPA protection. Clock management uses four fractional PLLs - PLL1 for CPU, PLL2 for DDR, PLL3/4 for peripherals - with independent frequency domains for power optimization.

Key Specifications

Pinout & Package

STM32MP133CAG3 is housed in a TFBGA289 package (9 × 9 mm, 0.5 mm pitch), with 289 solder balls arranged in a 17 × 17 grid (excluding corner dummy balls). Ball pitch and layout comply with JEDEC MO-271AB standard and support automated optical inspection (AOI) and X-ray void detection during reflow.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-core Arm Cortex-A7 microprocessor applications.

Compared with i.MX 8M Mini and RZ/G2L, the STM32MP133CAG3 uniquely combines dual CAN FD, dual IEEE 1588v2 Ethernet, and TrustZone-peripheral isolation in a single die-enabling consolidated edge gateway designs without external security co-processors or protocol bridges.

Availability

STM32MP133CAG3 is available at Aetrix Electronics and suitable for industrial HMI, smart building gateways, and edge AI vision nodes requiring stable component supply, long-term lifecycle assurance, and traceable sourcing for ISO 13485 and IEC 62443 compliance programs.

Supply support for STM32MP133CAG3 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power management ICs, MEMS, and automotive-grade processors with vertical fabrication capacity.

The STM32MP series targets heterogeneous computing for Linux-capable edge devices, combining real-time Cortex-M co-processors (in other variants) or bare-metal A7 subsystems with industrial-grade peripherals and hardware security for IIoT and smart infrastructure.

FAQ

What boot sources does the STM32MP133CAG3 support?

The STM32MP133CAG3 supports primary boot from eMMC/SD card, secondary boot from SPI NOR flash via QUADSPI, and fallback boot from UART or USB OTG. Boot mode is selected by BOOT0 pin state and internal OTP configuration, with secure boot enforced by BSEC and TrustZone address space controller before any code execution.

Does the STM32MP133CAG3 support DDR3L memory at 1066 MT/s?

Yes, the STM32MP133CAG3's DDRCTRL supports DDR3L-1066 (533 MHz clock) with 16-bit data bus width and configurable read/write leveling. Electrical characteristics specify tAC ≤ 0.45 ns and tDQSS ≤ 0.25 ns for reliable operation under industrial temperature range (–40°C to +105°C) with proper PCB stack-up and termination.

How many tamper detection pins are available, and what types are supported?

The STM32MP133CAG3 provides 12 dedicated tamper pins (TAMP1–TAMP12), including 5 active-tamper inputs with voltage-level monitoring and 7 passive-tamper inputs with edge detection. All tamper events trigger immediate secure domain reset and erase of sensitive keys stored in backup SRAM or OTP, per ST's AN5502 implementation guide.

Can the two Ethernet MACs operate simultaneously in different modes?

Yes, ETH1 and ETH2 support independent configurations: ETH1 can run in RGMII mode for full Gigabit throughput with IEEE 1588v2 hardware timestamping, while ETH2 operates in RMII mode for 10/100 Mbps management traffic. Both MACs share the same AXI interconnect but use separate DMA channels and interrupt vectors, enabling concurrent real-time and best-effort traffic handling.