STMicroelectronics STM32MP133DAE7
- Part No.:
- STM32MP133DAE7
- Manufacturer:
- STMicroelectronics
- Category:
- Microprocessors
- Package:
- 289-LFBGA
- Datasheet:
-
STM32MP133DAE7.pdf
- Description:
- Linear IC's
- Quantity:
- Payment:

- Shipping:

Inventory:3,532
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
STM32MP133DAE7 from STMicroelectronics is a dual-core Arm® Cortex®-A7 microprocessor unit (MPU) operating up to 1 GHz, featuring dual 10/100/1000 Mbps Ethernet MACs, dual CAN FD controllers, two 12-bit ADCs (5 Msps), and TrustZone® security. It integrates 128 KB L2 cache, 168 KB on-chip SRAM (128 KB AXI SYSRAM + 32 KB AHB SRAM + 8 KB backup SRAM), and supports LPDDR2/LPDDR3-1066 or DDR3/DDR3L-1066 external memory up to 1 Gbyte - deployed in industrial HMI, edge gateway, and secure IoT gateway applications.
For engineers reviewing the STM32MP133DAE7 datasheet, STM32MP133DAE7 pinout, STM32MP133DAE7 application, or STM32MP133DAE7 equivalent, key selection considerations include dual Ethernet + CAN FD coexistence, DDR retention in Standby mode, TrustZone-enabled peripheral isolation, and 135 secure GPIOs with wakeup capability.
Technical Context
The STM32MP133DAE7 implements a heterogeneous dual-core Arm Cortex-A7 subsystem with NEON and TrustZone, backed by a 128-KB unified L2 cache and independent 32-KB I/D L1 caches per core. Its interconnect comprises a 64-bit AXI bus matrix (266 MHz) and 32-bit AHB matrix (209 MHz), enabling concurrent high-bandwidth access to DDR, peripherals, and DMA resources.
Security is enforced at hardware level via TrustZone address space controller (TZC) for DDR, embedded tamper detection (12 pins, 5 active), BSEC OTP control, and cryptographic accelerators including HASH (SHA-256/512), ECDSA verification, true RNG (6 triple oscillators), and PKA. Power management includes five low-power modes (Sleep, Stop, LPLV-Stop, LPLV-Stop2, Standby) with DDR retention and sub-second RTC accuracy.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | Dual Arm Cortex-A7 @ up to 1 GHz - enables Linux-capable real-time processing with NEON SIMD and TrustZone memory/peripheral isolation. |
| Memory Interface | LPDDR2/LPDDR3-1066 or DDR3/DDR3L-1066, 16-bit bus, up to 1 Gbyte - supports cost-optimized, low-power DRAM for embedded Linux boot and runtime. |
| On-chip SRAM | 168 KB total: 128 KB AXI SYSRAM (cache-coherent), 32 KB AHB SRAM, 8 KB backup domain SRAM - enables fast boot code execution and secure context retention during power loss. |
| Communication Peripherals | 2× Gigabit Ethernet MAC (IEEE 1588v2, MII/RMII/RGMII), 2× CAN FD, 5× I2C, 8× UART/USART, 5× SPI, 2× SAI, SPDIF Rx - meets deterministic networking and audio I/O requirements in industrial gateways. |
| Analog & Timing | 2× 12-bit ADCs (5 Msps), DFSDM (4-channel sigma-delta filter), 24 timers (including 2× 32-bit advanced, 10× 16-bit general-purpose), secure RTC - supports motor control feedback, sensor fusion, and precise time-stamped event logging. |
| Security Features | TrustZone peripherals, 12× tamper pins (5 active), HASH (SHA-256/512), ECDSA, true RNG, 3072-bit fuses (96-bit UID) - enables secure boot, firmware attestation, and anti-tamper monitoring for certified industrial deployments. |
| Power Management | 1.71–3.6 V I/O supply (5 V-tolerant), POR/PDR/PVD/BOR, on-chip LDOs (1.8 V USB, 1.1 V core), backup regulator (~0.9 V), DDR retention in Standby - ensures robust operation across wide industrial voltage ranges and seamless low-power wake-up. |
Pinout & Package
STM32MP133DAE7 is packaged in TFBGA289 (9 × 9 mm, 0.5 mm pitch), compliant with ECOPACK2 environmental standards. This package provides 289 solder balls optimized for high-density PCB layouts while maintaining thermal and signal integrity for MPU-class performance.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDDCORE | Core power supply | 1.1 V nominal supply for CPU and L1/L2 cache logic; requires tight regulation and local decoupling for stable 1 GHz operation. |
| VDDQ_DDR | DDR I/O power | 1.2 V or 1.35 V supply for DDR interface; must be synchronized with DDR PHY timing and isolated from noisy digital domains. |
| NRST | Active-low reset input | Asynchronous reset assertion resets all internal logic; driven low for ≥20 µs to guarantee full system initialization after power-on or brownout. |
| BOOT0 | Boot mode selection | Sampled at power-up to select boot source (eMMC, SD, NAND, QSPI); tied high/low via external resistor for fixed configuration. |
| ETH1_RXD0–3 / ETH1_TXD0–3 | Gigabit Ethernet data lanes | Dedicated RMII/RGMII signals for first Ethernet MAC; require controlled impedance (50 Ω single-ended, 100 Ω differential) and length matching ≤5 mm. |
| FDCAN1_TX / FDCAN1_RX | CAN FD transceiver interface | Differential pair supporting bit rates up to 5 Mbps; must connect to ISO 11898-2 compliant physical layer with common-mode choke. |
Key Features
| Feature | Design Value |
|---|---|
| Dual Cortex-A7 with L2 cache | Enables symmetric multiprocessing (SMP) Linux execution while isolating real-time tasks in secure world via TrustZone. |
| DDR retention in Standby | Preserves full RAM content during ultra-low-power Standby mode (<100 µA), enabling instant resume without OS reload. |
| TrustZone address space controller (TZC) | Hardware-enforced memory firewall that partitions DDR into secure/non-secure regions, preventing unauthorized peripheral access. |
| Flexible clock architecture | Four fractional PLLs (PLL1–PLL4) allow independent frequency synthesis for CPU, DDR, audio, and USB domains - minimizing jitter and EMI. |
| Secure RTC with calendar | Hardware-accelerated BCD calendar and sub-second timestamping, powered from VBAT domain - maintains accurate time across full power cycles. |
Applications
| Industrial HMI Gateway | Smart Energy Meter Hub |
|---|---|
Use Scenario: Local touchscreen HMI with remote cloud connectivity, protocol translation (Modbus-to-MQTT), and fieldbus bridging (CAN FD to Ethernet). IC Role / Device Role / Timing Role: Primary application processor running Linux-based UI stack and protocol gateway services; synchronizes CAN FD timestamps with IEEE 1588v2 Ethernet clocks. Use Value: Dual Ethernet + dual CAN FD eliminates need for external bridge ICs; 128 KB L2 cache reduces Linux kernel latency; TrustZone secures OTA update verification. | Use Scenario: Multi-tenant energy meter aggregation node collecting data from 32+ smart meters via RS-485 and PLC, then forwarding via LTE/Ethernet. IC Role / Device Role / Timing Role: Central data concentrator MPU handling concurrent serial comms, secure TLS offload, and time-synchronized load profiling using RTC calendar. Use Value: 135 secure GPIOs support direct RS-485 transceiver control and tamper detection; DFSDM processes sigma-delta current sensors; backup SRAM retains billing counters during mains failure. |
| Secure Edge AI Gateway | Railway Signaling Controller |
Use Scenario: On-train inferencing gateway performing anomaly detection on vibration/sensor streams, with encrypted model updates and secure log export. IC Role / Device Role / Timing Role: Trusted execution environment host for AI inference runtime; uses PKA and HASH for signed model validation and secure boot chain enforcement. Use Value: ECDSA verification accelerates firmware signature checks; true RNG seeds TLS handshakes; tamper pins detect enclosure breach during maintenance. | Use Scenario: EN 5012x-certified signaling controller interfacing with track circuits, axle counters, and interlocking systems via CAN FD and discrete I/O. IC Role / Device Role / Timing Role: SIL-2-capable safety monitor executing watchdog-checked application logic; uses independent watchdogs (IWDG1/IWDG2) and secure RTC for event sequence logging. Use Value: Dual independent watchdogs enable cross-monitoring; temperature/voltage/frequency monitors feed diagnostic reports; LPLV-Stop2 mode supports battery-backed fail-safe state retention. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar MPU-based industrial gateway applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| NXP i.MX 8M Mini (LPC55S69) | Single Cortex-A53 core (1.8 GHz), no TrustZone-peripheral isolation, lacks dual CAN FD and IEEE 1588v2 Ethernet hardware support. | Better suited for multimedia-rich UIs; weaker for deterministic dual-network coexistence and functional safety monitoring. | Select when higher single-thread CPU throughput is prioritized over dual-CAN FD timing determinism and hardware-assisted security partitioning. |
| Renesas RZ/G2L (R9A07G043L2) | Dual Cortex-A55 (1.2 GHz), includes 3D GPU and video codec; no built-in DFSDM or dedicated tamper pins; TrustZone implementation differs in peripheral gating granularity. | Stronger for vision-based HMI; less optimized for analog sensor fusion and physical tamper response in harsh environments. | Prefer when camera input, GUI acceleration, or video streaming are primary; avoid when sigma-delta sensor processing or active tamper detection are mandatory. |
Compared with i.MX 8M Mini and RZ/G2L, the STM32MP133DAE7 delivers tighter integration of dual CAN FD + dual Ethernet with hardware IEEE 1588v2, on-die DFSDM for current sensing, and 5 active tamper inputs - making it uniquely suited for safety-critical, sensor-rich industrial gateways requiring deterministic I/O and verified secure boot.
Availability
STM32MP133DAE7 is available at Aetrix Electronics and suitable for industrial HMI, smart energy metering, secure edge AI gateways, and railway signaling controllers requiring stable component supply across extended product lifecycles.
Supply support for STM32MP133DAE7 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power ICs, sensors, and automotive-grade components with emphasis on energy efficiency and functional safety.
The STM32MP series targets Linux-capable, security-aware edge devices - combining real-time MCU heritage with application processor performance, specifically engineered for industrial automation, building control, and infrastructure monitoring.
FAQ
What boot sources does the STM32MP133DAE7 support?
The STM32MP133DAE7 supports boot from eMMC, SD card, Quad-SPI NOR flash, and parallel NAND flash via configurable BOOT0/BOOT1 pins. Boot ROM firmware validates signed images using ECDSA and loads FSBL (First Stage Boot Loader) into SYSRAM before initializing DDR and launching U-Boot or TF-A. No external boot EEPROM is required.
Does the STM32MP133DAE7 include hardware support for IEEE 1588v2 Precision Time Protocol?
Yes - both integrated Ethernet MACs (ETH1 and ETH2) include full IEEE 1588v2 hardware timestamping engines with sub-nanosecond resolution, PTP event message filtering, and hardware-assisted delay measurement. This enables deterministic time synchronization in industrial automation and power grid applications without CPU overhead.
How is TrustZone implemented for peripheral protection on this device?
TrustZone is implemented through the Embedded TrustZone Protection Controller (ETZPC), which gates access to peripherals (e.g., UART, SPI, CAN) based on secure/non-secure world privilege. Combined with the TrustZone Address Space Controller (TZC) for DDR memory partitioning, it enforces hardware-isolated execution environments - critical for secure boot, firmware updates, and confidential data handling.
What is the maximum DDR memory bandwidth supported by the STM32MP133DAE7?
The STM32MP133DAE7 DDR controller supports LPDDR2/LPDDR3-1066 or DDR3/DDR3L-1066 at 16-bit bus width, delivering up to 2.1 GB/s peak theoretical bandwidth (1066 MT/s × 2 bytes). Real-world sustained bandwidth depends on PHY tuning, PCB layout, and memory vendor timing parameters - validated up to 1 Gbyte density in ST reference designs.
STM32MP133DAE7 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Package/Case:
- 289-LFBGA
- Series:
- STM32MP1
- Packaging:
- Tray
- Product Status:
- Active
- Core Processor:
- ARM® Cortex®-A7
- Number of Cores/Bus Width:
- 1 Core, 32-Bit
- Speed:
- 1GHz
- Co-Processors/DSP:
- Multimedia; NEON™ SIMD
- RAM Controllers:
- DDR3, DDR3L, LPDDR2, LPDDR3
- Graphics Acceleration:
- Yes
- Display & Interface Controllers:
- LCD
- Ethernet:
- 10/100/1000Mbps (2)
- SATA:
- -
- USB:
- USB 2.0 (2)
- Voltage - I/O:
- 1.8V, 2.5V, 3.3V
- Operating Temperature:
- -40°C ~ 105°C (TJ)
- Grade:
- -
- Qualification:
- -
- Security Features:
- AES, ARM TZ, Boot Security, Cryptography, Secure Debug, SHA-1/2, Tamper Detection, TRNG, Volatile key Storage
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 289-LFBGA (14x14)
- Additional Interfaces:
- CANbus, GPIO, I2C, I2S, IrDA, MMC/SD/SDIO, SAI, SPDIF, SPI, UART/USART
STM32MP133DAE7 FAQ
1.How can I place an order for STM32MP133DAE7 through Aetrix?
Please submit a Request for Quotation (RFQ) for STM32MP133DAE7 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for STM32MP133DAE7 reliable?
The price and inventory of STM32MP133DAE7 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for STM32MP133DAE7 is usually 5 days.
3.What payment methods are accepted for STM32MP133DAE7?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for STM32MP133DAE7 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for STM32MP133DAE7?
STM32MP133DAE7 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your STM32MP133DAE7 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for STM32MP133DAE7?
For technical support, including STM32MP133DAE7 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your STM32MP133DAE7 requirements.
6.How does Aetrix verify that STM32MP133DAE7 is sourced from the original manufacturer or authorized distributors?
All STM32MP133DAE7 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that STM32MP133DAE7 meets industry standards.
7.What is the process for return or replacement of STM32MP133DAE7?
All STM32MP133DAE7 units undergo pre-shipment inspection (PSI). If there is an issue with STM32MP133DAE7, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The STM32MP133DAE7 part is unused and in its original packaging.
Return procedure for STM32MP133DAE7:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
STM32MP133DAE7 Tags

-
AT91SAM9260B-CU-999
Microchip Technology

-
AT91SAM9G25-CU
Microchip Technology

-
ATSAMA5D27C-CU
Microchip Technology

-
AT91SAM9X35-CU
Microchip Technology

-
AT91SAM9X25-CU
Microchip Technology

-
MCIMX6Y2CVM08AB
NXP Semiconductors
-
AM3352BZCZ100
Texas Instruments

-
AT91SAM9260B-CU
Microchip Technology

-
AT91SAM9260B-QU
Microchip Technology

-
ATSAMA5D31A-CU
Microchip Technology

-
AT91SAM9G20B-CU-999
Microchip Technology

-
MCIMX6Y2CVM05AB
NXP Semiconductors
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

