STMicroelectronics STM32MP133DAE7T

Overview

STM32MP133DAE7T from STMicroelectronics is a dual-core Arm® Cortex®-A7 microprocessor operating up to 1 GHz, featuring dual Ethernet MAC/GMAC (IEEE 1588v2), dual CAN FD controllers, two 12-bit ADCs (5 Msps), and TrustZone® security. It integrates 128 KB L2 cache, 168 KB on-chip SRAM (128 KB AXI SYSRAM + 32 KB AHB SRAM + 8 KB Backup SRAM), and supports LPDDR2/LPDDR3-1066 or DDR3/DDR3L-1066 external memory up to 1 Gbyte - deployed in industrial HMI, edge gateway, and secure IoT gateway applications.

For engineers reviewing the STM32MP133DAE7T datasheet, STM32MP133DAE7T pinout, STM32MP133DAE7T application, or STM32MP133DAE7T equivalent, key selection considerations include dual-CPU clocking architecture, DDR controller timing compliance, CAN FD bit-rate configurability (up to 5 Mbit/s), Ethernet RGMII/MII/RMII interface support, and TrustZone-enabled peripheral isolation for secure boot and runtime partitioning.

Technical Context

The STM32MP133DAE7T implements a dual-core Arm Cortex-A7 subsystem with independent L1 I/D caches (32 KB each), unified 128 KB L2 cache, NEON™ SIMD extension, and hardware-enforced TrustZone® for secure world/non-secure world separation. Its interconnect matrix comprises a 64-bit AXI bus (266 MHz) and 32-bit AHB bus (209 MHz), enabling concurrent high-bandwidth peripheral access.

It features four fractional PLLs (PLL1–PLL4) supporting dynamic frequency scaling across CPU, AXI, AHB, and peripheral domains; dual Ethernet MACs with IEEE 1588v2 timestamping and hardware TSN readiness; and dual CAN FD controllers compliant with ISO 11898-1:2015, supporting data phase bit rates up to 5 Mbit/s and flexible transceiver-independent configuration.

Key Specifications

Pinout & Package

STM32MP133DAE7T uses a TFBGA289 package (9 mm × 9 mm, 0.5 mm pitch, B0EB variant), RoHS-compliant and ECOPACK2 certified. Pin count: 289 balls. Thermal resistance θ_JA = 26.5 °C/W (JEDEC standard board).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-core Arm Cortex-A7 microprocessor applications.

Compared with STM32MP133DAE7T, STM32MP157CAA3 lacks CAN FD and dual Ethernet - limiting fieldbus bridging - while i.MX 8M Mini offers higher CPU throughput but introduces PMIC dependency and looser real-time control over peripheral security domains.

Availability

STM32MP133DAE7T is available at Aetrix Electronics and suitable for industrial HMI, edge gateway, and secure IoT gateway applications requiring stable component supply, long-term lifecycle assurance, and full production traceability.

Supply support for STM32MP133DAE7T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, specializing in microcontrollers, power management, sensors, and automotive ICs with strong industrial and IoT focus.

The STM32MP series targets heterogeneous computing for Linux-capable embedded systems, combining real-time Cortex-M co-processors (in other variants) or bare-metal Cortex-A use cases with hardware security and industrial interface richness - designed specifically for deterministic edge intelligence.

FAQ

What boot sources does STM32MP133DAE7T support?

STM32MP133DAE7T supports boot from Quad-SPI flash, SD/eMMC, NAND flash via FMC, USB device, UART, and internal ROM. Boot mode is configured via BOOT0/BOOT1 pins, and the first-stage bootloader (FSBL) resides in embedded ROM with verified secure boot chain including hash verification and public-key signature check using BSEC-stored keys.

Does STM32MP133DAE7T include an integrated PMIC?

No, STM32MP133DAE7T does not integrate a full PMIC but includes on-die LDOs for USB PHY (1.8 V), core (1.1 V), and backup domain (~0.9 V). External PMIC (e.g., STPMIC1) is recommended for complete power sequencing, DDR termination regulation, and dynamic voltage scaling across VDDCORE/VDDCPU/VDDQ_DDR rails.

How is TrustZone implemented for peripheral access control?

TrustZone implementation uses the ETZPC (Embedded TrustZone Protection Controller) to assign each peripheral to secure or non-secure world at reset. Access attempts from non-secure software to secure peripherals generate bus errors, enforced by hardware - no software intervention required. Configuration is locked after boot via BSEC fuses.

What is the maximum DDR bandwidth achievable with STM32MP133DAE7T?

With DDR3L-1066 (533 MHz clock, 16-bit bus), STM32MP133DAE7T achieves up to 8.5 GB/s theoretical peak bandwidth. Real-world sustained bandwidth depends on AXI arbitration, L2 cache hit rate, and DDR PHY tuning - measured at ~5.2 GB/s in typical Linux kernel memory copy benchmarks using optimized memcpy routines.