STMicroelectronics STM32MP133DAG7T

Overview

STM32MP133DAG7T from STMicroelectronics is a dual-core Arm® Cortex®-A7 microprocessor operating up to 1 GHz, featuring 2× Ethernet MAC/GMAC (IEEE 1588v2), 2× CAN FD controllers, 2× 12-bit ADCs (5 Msps), and TrustZone® security. It integrates 128 KB L2 cache, 168 KB on-chip SRAM (AXI/AHB/Backup domains), and supports LPDDR2/LPDDR3-1066 or DDR3/DDR3L-1066 external memory - deployed in industrial HMI, edge gateway, and secure IoT gateway applications.

For engineers reviewing the STM32MP133DAG7T datasheet, STM32MP133DAG7T pinout, STM32MP133DAG7T application, or STM32MP133DAG7T equivalent, key selection criteria include dual-Cortex-A7 performance with hardware virtualization support, integrated CAN FD + Gigabit Ethernet coexistence, TrustZone-enabled peripheral isolation, and TFBGA289 (9 × 9 mm, 0.5 mm pitch) package compatibility with industrial thermal and layout constraints.

Technical Context

The STM32MP133DAG7T implements a heterogeneous dual-core Arm Cortex-A7 subsystem with independent L1 I/D caches (32 KB each), unified 128 KB L2 cache, NEON™ SIMD acceleration, and TrustZone® for secure world/non-secure world partitioning. Its interconnect comprises a 64-bit AXI bus matrix (266 MHz) and 32-bit AHB matrix (209 MHz), enabling concurrent high-bandwidth peripheral access.

It integrates four fractional PLLs (PLL1–PLL4) for precise clock domain separation: PLL1 drives CPU cores, PLL2 feeds AXI/AHB buses and peripherals, PLL3/PLL4 serve audio (SAI/SPDIF) and USB, respectively. The device supports boot from Quad-SPI, SDMMC, NAND, or USB, with BSEC-managed OTP fuses (3072-bit, including 96-bit UID) for secure boot and key storage.

Key Specifications

Pinout & Package

STM32MP133DAG7T is packaged in TFBGA289 (9 × 9 mm, 0.5 mm pitch, B0EB marking), RoHS-compliant and ECOPACK2 certified. Pinout conforms to ST's official ball map (DS13876 Rev 7, Table 7), with 289 solder balls arranged in 17 × 17 grid (corner balls omitted). Key signal groups include: 135 secure GPIOs (with interrupt/wakeup capability), dual 16-bit DDR data bus (DQ0–DQ15), dual RMII/RGMII interfaces (TX/RX clocks, data, CRS, COL), CAN FD transceiver pins (CAN_RX1/2, CAN_TX1/2), and dedicated TrustZone-protected debug (SWD/JTAG) and boot configuration balls.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-core Arm Cortex-A7 microprocessor applications.

Compared with STM32MP133DAG7T, STM32MP135DAA3 offers identical functionality in a more manufacturable package but omits SPDIF Rx, while i.MX 8M Mini trades deterministic dual-A7 timing and integrated CAN FD for higher general-purpose compute - making STM32MP133DAG7T preferable for time-sensitive industrial gateways requiring hardware-enforced security and protocol coexistence.

Availability

STM32MP133DAG7T is available at Aetrix Electronics and suitable for industrial HMI, edge gateway, and secure IoT gateway applications requiring stable component supply, long-term lifecycle assurance, and full production traceability.

Supply support for STM32MP133DAG7T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power management ICs, sensors, and automotive-grade components since 1987.

The STM32MP series targets Linux-capable embedded applications demanding real-time responsiveness, hardware security, and heterogeneous processing - specifically engineered for industrial automation, smart infrastructure, and secure edge computing.

FAQ

What boot sources does the STM32MP133DAG7T support?

The STM32MP133DAG7T supports boot from Quad-SPI flash, SD/eMMC, SLC NAND, USB mass storage, and UART. Boot mode is selected via BOOT0 and BOOT1 pins at power-on reset, with configuration latched and validated by the ROM code before loading FSBL. External memory initialization (e.g., DDR training) is handled by the first-stage bootloader.

Does the STM32MP133DAG7T include hardware support for CAN FD bit rate switching?

Yes - both FDCAN1 and FDCAN2 controllers natively implement ISO 11898-1:2015 compliant CAN FD with automatic bit rate switching (BRS). Each controller supports programmable data phase bit rates up to 5 Mbit/s, configurable TDC (Transmitter Delay Compensation), and flexible data length (up to 64 bytes), verified in DS13876 §3.37 and electrical characteristics §6.3.32.

How is TrustZone implemented for peripheral protection on this device?

TrustZone is enforced via the ETZPC (Embedded TrustZone Protection Controller), which assigns each peripheral to secure or non-secure state at reset. Access permissions are configured through dedicated registers (TZPC_PERx), and violations trigger secure interrupts. Critical peripherals like RNG, HASH, and tamper pins are hardwired as secure-only, while GPIOs and UARTs support dynamic assignment via software-controlled TZIC.

What is the maximum DDR memory bandwidth achievable with the STM32MP133DAG7T?

With DDR3L-1066 (16-bit bus), the STM32MP133DAG7T achieves a theoretical peak bandwidth of 2.13 GB/s (1066 MT/s × 2 bytes). Real-world sustained bandwidth depends on AXI bus arbitration, L2 cache hit rate, and DDR controller tuning - measured at ≥1.6 GB/s in ST's MP13-EV1 evaluation platform under Linux dd benchmark with 128 MB transfers.