STMicroelectronics STM32MP133FAE7
- Part No.:
- STM32MP133FAE7
- Manufacturer:
- STMicroelectronics
- Category:
- Microprocessors
- Package:
- 289-LFBGA
- Datasheet:
-
STM32MP133FAE7.pdf
- Description:
- Linear IC's
- Quantity:
- Payment:

- Shipping:

Inventory:4,031
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
STM32MP133FAE7 from STMicroelectronics is a dual-core Arm® Cortex®-A7 microprocessor operating up to 1 GHz, featuring dual Ethernet MAC/GMAC (IEEE 1588v2), dual CAN FD controllers, dual 12-bit ADCs (5 Msps), hardware crypto acceleration (AES-128/192/256, SHA-256/512, PKA), and TrustZone®-enabled secure boot. It targets industrial HMI, edge gateway, and smart building control systems requiring real-time connectivity, audio processing, and tamper-resistant firmware execution.
For engineers reviewing the STM32MP133FAE7 datasheet, STM32MP133FAE7 pinout, STM32MP133FAE7 application, or STM32MP133FAE7 equivalent, key selection considerations include DDR3/LPDDR3 memory interface timing, CAN FD bit-rate configuration, TrustZone peripheral partitioning, and LFBGA289 (14 × 14 mm, 0.8 mm pitch) mechanical layout constraints.
Technical Context
The device integrates two Arm Cortex-A7 cores with 32 KB I-cache / 32 KB D-cache each and a shared 128 KB L2 cache, supporting Linux-based OS execution and real-time RTOS cohabitation via TrustZone isolation. Its interconnect matrix comprises a 64-bit AXI bus (266 MHz) and 32-bit AHB bus (209 MHz), enabling concurrent high-bandwidth DDR access and low-latency peripheral control.
Clock architecture includes four fractional PLLs - PLL1 for CPU clocking, PLL2 for DDR, PLL3 for peripherals, and USB_PLL - with independent frequency domains and spread-spectrum support. Security subsystems comprise BSEC OTP fuses (3072-bit), ETZPC address space controller, TZC for DDR protection, and 12 tamper pins (5 active) for physical intrusion detection.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | Dual Arm Cortex-A7 @ up to 1 GHz; enables Linux + RTOS dual-world execution with TrustZone isolation |
| Memory Interface | 16-bit DDR3/DDR3L-1066 or LPDDR2/LPDDR3-1066; supports up to 1 Gbyte external SDRAM for OS and application code |
| Security Features | Secure boot, TrustZone peripherals, 12 tamper pins (5 active), 3072-bit OTP fuses including 256-bit HUK for AES-256 key protection |
| Connectivity | 2× Ethernet MAC/GMAC (MII/RMII/RGMII, IEEE 1588v2), 2× CAN FD, 5× I2C, 8× UART/USART, 5× SPI, 2× SDMMC, 2× USB 2.0 HS (Host + OTG) |
| Analog & Timing | 2× 12-bit ADCs (5 Msps), 24 timers (including 2× 32-bit advanced, 10× 16-bit general-purpose), secure RTC with sub-second accuracy |
| Package | LFBGA289 (14 × 14 mm, 0.8 mm pitch); RoHS-compliant ECOPACK2 package with thermal pad for industrial-grade thermal management |
| Power Management | 1.71–3.6 V I/O supply (5 V-tolerant), on-chip LDOs (1.8 V USB, 1.1 V core), DDR retention in Standby mode, 5 low-power modes |
Pinout & Package
LFBGA289 (14 × 14 mm, 0.8 mm pitch) package with exposed thermal pad; 289 solder balls arranged in 17 × 17 array with corner missing; compatible with standard reflow profiles and industrial PCB assembly processes.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDDCORE | Core power supply | 1.1 V nominal supply for CPU and L1/L2 cache; requires low-noise regulation and local decoupling |
| VDDQ_DDR | DDR I/O power | 1.2 V or 1.35 V supply for DDR data/address bus; critical for signal integrity and timing margin |
| NRST | Active-low reset input | Synchronous reset assertion with internal pull-up; must be held low ≥ 20 µs for full system reset |
| BOOT0 | Boot mode selection | High at power-up selects internal ROM bootloader; tied low for user flash or external memory boot |
| ETH1_RXD0–ETH1_RXD3 | Ethernet receive data | RMII/RGMII-compatible inputs; require matched trace lengths ≤ 50 mm and 50 Ω termination |
| FDCAN1_TX / FDCAN1_RX | CAN FD transceiver interface | Differential pair supporting up to 5 Mbps bit rate; needs common-mode choke and 120 Ω termination |
Key Features
| Feature | Design Value |
|---|---|
| Arm NEON™ SIMD engine | Accelerates audio codec, image processing, and ML inference kernels without offloading to external DSP |
| On-the-fly DRAM encryption | AES-128 encryption/decryption of DDR traffic in real time, preventing cold-boot and DMA-based memory snooping |
| Dual Quad-SPI interface | Supports XIP (execute-in-place) from two independent serial flash devices, reducing boot latency and BOM cost |
| SAI + SPDIF interfaces | Enables stereo audio playback (I2S/PDM) and multi-channel digital audio input (SPDIF Rx with 4 inputs) for voice-enabled HMI |
| DFSDM with 4 channels | Digital filter for sigma-delta modulators allows direct connection to MEMS microphones or current-sense sensors without external ADC |
Applications
| Industrial HMI Panel | Smart Building Gateway |
|---|---|
Use Scenario: Touchscreen-based operator interface for PLC-controlled HVAC and lighting systems. IC Role / Device Role / Timing Role: Main application processor running embedded Linux UI stack, managing display, touch, Ethernet, and CAN FD fieldbus communication. Use Value: Dual Cortex-A7 cores enable concurrent UI rendering and real-time CAN FD message handling without jitter; TrustZone isolates firmware update logic from user applications. | Use Scenario: Protocol translation hub aggregating Modbus RTU, KNX, and BACnet MS/TP devices into cloud-connected IP network. IC Role / Device Role / Timing Role: Central protocol gateway processor with dual Ethernet ports (LAN/WAN), dual CAN FD for legacy fieldbus bridging, and hardware crypto for TLS 1.3 endpoint security. Use Value: IEEE 1588v2 hardware timestamping ensures deterministic synchronization across distributed building controllers; AES-256 + PKA accelerates certificate-based authentication. |
| Edge AI Vision Node | Secure Industrial Router |
Use Scenario: Low-power vision inspection node using MIPI CSI-2 camera input and neural network inference for defect detection. IC Role / Device Role / Timing Role: Vision processing SoC executing lightweight CNN models via NEON-accelerated libraries, feeding results over Ethernet or CAN FD to supervisory PLC. Use Value: 5 Msps dual ADCs support analog sensor fusion (temperature, vibration); DFSDM channels interface directly to sigma-delta pressure/flow sensors. | Use Scenario: Ruggedized router deployed in remote substations with cellular failover, firewall, and encrypted VPN tunneling. IC Role / Device Role / Timing Role: Secure networking processor managing dual Ethernet WAN/LAN, USB host for 4G modem, and hardware-accelerated IPsec/IKEv2. Use Value: On-chip RNG and HASH engines meet FIPS 140-2 Level 1 requirements for cryptographic key generation and integrity verification; tamper pins detect enclosure breach and trigger secure erase. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-core Arm Cortex-A7 microprocessor applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| STM32MP157C-DK2 | Single Cortex-A7 core (up to 800 MHz), no CAN FD, lower DDR bandwidth (LPDDR2 only), larger TFBGA320 package | Targeted at cost-sensitive HMI with basic connectivity; lacks dual Ethernet and advanced security features | Select when CAN FD and IEEE 1588v2 are not required, and BOM cost is prioritized over feature density |
| i.MX 8M Mini (NXP) | Quad Cortex-A53 + Cortex-M4, supports eMMC 5.1, PCIe, but no integrated CAN FD or TrustZone-peripheral granularity | Better multimedia throughput and GPU acceleration; weaker real-time fieldbus integration and secure boot configurability | Prefer for Android-based UI or video streaming; avoid when deterministic CAN FD timing and fine-grained TrustZone peripheral control are mandatory |
Compared with STM32MP133FAE7, STM32MP157C-DK2 offers lower cost and simpler power sequencing but omits CAN FD and dual-GMAC; i.MX 8M Mini delivers higher CPU throughput and GPU capability yet requires external CAN transceivers and lacks ST's integrated tamper detection and BSEC OTP structure.
Availability
STM32MP133FAE7 is available at Aetrix Electronics and suitable for industrial HMI, smart building gateways, and secure edge routers requiring stable component supply, long-term lifecycle assurance, and qualified automotive/industrial temperature grade availability.
Supply support for STM32MP133FAE7 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, specializing in microcontrollers, power management, sensors, and automotive ICs with strong industrial and embedded systems focus.
The STM32MP series is designed for heterogeneous multicore applications combining Linux-capable application processors with real-time microcontroller functionality, targeting industrial automation, energy infrastructure, and secure IoT edge nodes.
FAQ
What is the maximum DDR3/LPDDR3 speed supported by STM32MP133FAE7?
The STM32MP133FAE7 supports DDR3/DDR3L-1066 and LPDDR2/LPDDR3-1066, meaning it operates with a 533 MHz clock (1066 MT/s data rate) on a 16-bit bus. This provides up to 1.7 GB/s peak bandwidth, sufficient for Linux kernel, GUI frameworks, and real-time application buffers. The DDR controller includes configurable read/write leveling and per-byte write calibration.
Does STM32MP133FAE7 support CAN FD with ISO 11898-1:2015 compliance?
Yes, both FDCAN1 and FDCAN2 controllers fully comply with ISO 11898-1:2015, supporting bit rates up to 5 Mbps in FD mode, flexible data-length payloads (up to 64 bytes), and automatic protocol arbitration. Each controller includes dedicated Tx/Rx FIFOs, error counters, and loopback self-test modes verified in ST's qualification test plan.
How is TrustZone implemented for peripheral protection on this device?
TrustZone is enforced via the ETZPC (Embedded TrustZone Protection Controller), which assigns each peripheral to Secure or Non-Secure world at boot. Configuration is stored in BSEC OTP and locked after first write. Peripherals like UART, SPI, and timers can be individually gated, while memory-mapped registers are protected by AXI bus-level address filtering through the TZC (TrustZone Address Space Controller).
What thermal design guidance applies to the LFBGA289 package?
The LFBGA289 package (14 × 14 mm) requires a 6-layer PCB with dedicated thermal vias under the exposed pad (minimum 9 vias, 0.3 mm diameter, filled or capped) connecting to internal ground planes. ST specifies θJA = 28.5 °C/W (JEDEC JESD51-7, 4-layer board) and recommends maintaining junction temperature ≤ 105 °C under worst-case 1 GHz load with 100% CPU utilization and DDR activity.
STM32MP133FAE7 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Package/Case:
- 289-LFBGA
- Series:
- STM32MP1
- Packaging:
- Tray
- Product Status:
- Active
- Core Processor:
- ARM® Cortex®-A7
- Number of Cores/Bus Width:
- 1 Core, 32-Bit
- Speed:
- 1GHz
- Co-Processors/DSP:
- Multimedia; NEON™ SIMD
- RAM Controllers:
- DDR3, DDR3L, LPDDR2, LPDDR3
- Graphics Acceleration:
- Yes
- Display & Interface Controllers:
- LCD
- Ethernet:
- 10/100/1000Mbps (2)
- SATA:
- -
- USB:
- USB 2.0 (2)
- Voltage - I/O:
- 1.8V, 2.5V, 3.3V
- Operating Temperature:
- -40°C ~ 105°C (TJ)
- Grade:
- -
- Qualification:
- -
- Security Features:
- AES, ARM TZ, Boot Security, Cryptography, Secure Debug, SHA-1/2, Tamper Detection, TRNG, Volatile key Storage
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 289-LFBGA (14x14)
- Additional Interfaces:
- CANbus, GPIO, I2C, I2S, IrDA, MMC/SD/SDIO, SAI, SPDIF, SPI, UART/USART
STM32MP133FAE7 FAQ
1.How can I place an order for STM32MP133FAE7 through Aetrix?
Please submit a Request for Quotation (RFQ) for STM32MP133FAE7 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for STM32MP133FAE7 reliable?
The price and inventory of STM32MP133FAE7 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for STM32MP133FAE7 is usually 5 days.
3.What payment methods are accepted for STM32MP133FAE7?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for STM32MP133FAE7 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for STM32MP133FAE7?
STM32MP133FAE7 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your STM32MP133FAE7 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for STM32MP133FAE7?
For technical support, including STM32MP133FAE7 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your STM32MP133FAE7 requirements.
6.How does Aetrix verify that STM32MP133FAE7 is sourced from the original manufacturer or authorized distributors?
All STM32MP133FAE7 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that STM32MP133FAE7 meets industry standards.
7.What is the process for return or replacement of STM32MP133FAE7?
All STM32MP133FAE7 units undergo pre-shipment inspection (PSI). If there is an issue with STM32MP133FAE7, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The STM32MP133FAE7 part is unused and in its original packaging.
Return procedure for STM32MP133FAE7:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
STM32MP133FAE7 Tags

-
AT91SAM9260B-CU-999
Microchip Technology

-
AT91SAM9G25-CU
Microchip Technology

-
ATSAMA5D27C-CU
Microchip Technology

-
AT91SAM9X35-CU
Microchip Technology

-
AT91SAM9X25-CU
Microchip Technology

-
MCIMX6Y2CVM08AB
NXP Semiconductors
-
AM3352BZCZ100
Texas Instruments

-
AT91SAM9260B-CU
Microchip Technology

-
AT91SAM9260B-QU
Microchip Technology

-
ATSAMA5D31A-CU
Microchip Technology

-
AT91SAM9G20B-CU-999
Microchip Technology

-
MCIMX6Y2CVM05AB
NXP Semiconductors
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

