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STMicroelectronics STM32MP133FAG7

Name: STM32MP133FAG7
Brand: STMicroelectronics
SKU: STM32MP133FAG7
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: STM32MP133FAG7

Manufacturer:: STMicroelectronics

Category:: Microprocessors

Package:: 289-TFBGA

Datasheet:: STM32MP133FAG7.pdf

Description:: Linear IC's

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Product details

Overview

STM32MP133FAG7 from STMicroelectronics is a dual-core Arm® Cortex®-A7 microprocessor operating up to 1 GHz, featuring dual 10/100/1000 Mbps Ethernet MACs, dual CAN FD controllers, two 12-bit ADCs (5 Msps), hardware crypto acceleration (AES-256, SHA-512, PKA), and TrustZone®-enabled security. It integrates 128 KB L2 cache, 168 KB on-chip SRAM (128 KB AXI SYSRAM + 32 KB AHB SRAM + 8 KB Backup SRAM), and supports LPDDR3-1066/DDR3L-1066 external memory - deployed in industrial HMIs, edge gateways, and secure IoT edge nodes.

For engineers reviewing the STM32MP133FAG7 datasheet, STM32MP133FAG7 pinout, STM32MP133FAG7 application, or STM32MP133FAG7 equivalent, key selection criteria include dual-CAN FD timing integrity, IEEE 1588v2 PTP support in both Ethernet MACs, DDR retention in Standby mode, TrustZone peripheral isolation, and hardware-accelerated DRAM encryption for secure boot and runtime protection.

Technical Context

The STM32MP133FAG7 implements a heterogeneous dual-core Arm Cortex-A7 subsystem with shared 128 KB unified L2 cache, NEON™ SIMD extension, and full TrustZone® address space partitioning. Its interconnect comprises a 64-bit AXI bus matrix (266 MHz) and 32-bit AHB matrix (209 MHz), enabling concurrent high-bandwidth peripheral access.

Security architecture includes BSEC OTP fuses (3072 bits, 96-bit UID, 256-bit HUK), tamper detection (12 pins, 5 active), secure boot with hash-based signature verification, and TZC-controlled DDR memory firewalling. Clocking uses four fractional PLLs - PLL1 for CPU, PLL2 for peripherals, PLL3/4 for audio/USB - with spread-spectrum support and HSE/LSE monitoring.

Key Specifications

Parameter	Value and Actual Design Meaning
CPU Core	Dual Arm® Cortex®-A7 @ up to 1 GHz - enables Linux-capable real-time edge processing with NEON and TrustZone
Memory Interface	LPDDR2/LPDDR3-1066 or DDR3/DDR3L-1066 (16-bit, up to 1 Gbyte) - supports low-power, high-throughput external DRAM
On-chip SRAM	168 KB total: 128 KB AXI SYSRAM (cache-coherent), 32 KB AHB SRAM, 8 KB Backup domain SRAM - enables fast context switching and RTC-critical data retention
Security Features	TrustZone®, AES-128/192/256 + DPA protection, PKA (ECC/RSA), SHA-224/256/384/512, TRNG (6 oscillators), 3072-bit OTP - meets IEC 62443-3-3 SL2 requirements
Communication Peripherals	2× FDCAN, 2× Gigabit Ethernet (MII/RMII/RGMII, IEEE 1588v2), 5× I2C, 8× UART/USART, 5× SPI, 2× SAI, SPDIF-Rx - supports deterministic fieldbus + time-sensitive networking
Analog & Timing	2× 12-bit ADC (5 Msps), DFSDM (4-channel sigma-delta filter), 24 timers including 2× 32-bit quadrature encoder timers, secure RTC - enables motor control feedback and precision timestamping
Power Management	1.71–3.6 V I/O supply (5 V-tolerant), LPLV-Stop2/Standby modes, DDR retention in Standby, internal LDOs (1.1 V, 1.8 V), backup regulator (~0.9 V) - ensures robust operation across industrial voltage ranges

Pinout & Package

LFBGA289 package (14 × 14 mm, 0.8 mm pitch), RoHS-compliant and ECOPACK2 certified. Ball grid layout optimized for signal integrity in high-speed DDR and Ethernet routing, with dedicated power/ground ball patterns and controlled impedance trace routing guidance per ST's AN5027.

Pin/Terminal	Circuit Role	Design Meaning
VDDCORE	Core power supply	1.1 V ±5% supply for Cortex-A7 cores and L2 cache - requires low-noise regulation and local decoupling
VDDCPU	CPU domain power	1.1 V supply dedicated to CPU subsystem - independent from VDDCORE for dynamic voltage scaling
VDDQ_DDR	DDR I/O power	1.2 V or 1.35 V supply for DDR interface - must track DDR standard voltage and slew rate requirements
ETH1_RXD[3:0]/TXD[3:0]	Gigabit Ethernet PHY interface	RMII/RGMII-compatible differential pairs - requires 50 Ω single-ended / 100 Ω differential impedance routing
FDCAN1_TX/RX	CAN FD transceiver interface	High-speed differential signaling (up to 5 Mbps) - needs common-mode choke and 120 Ω termination
BOOT0	Boot mode selection	Active-high strap pin sampled at reset - determines boot source (FSMC, QSPI, SDMMC, USB, UART)
NRESET	System reset input	Asynchronous active-low reset - synchronized internally; minimum pulse width 20 ns
OSC_IN/OSC_OUT	HSE oscillator connection	8–48 MHz crystal interface - supports analog/digital bypass modes and CSS fault detection

Key Features

Feature	Design Value
Dual Cortex-A7 with L2 cache	Enables SMP Linux execution with deterministic latency for real-time tasks via CPU affinity and interrupt steering
TrustZone-enabled peripherals	Allows secure world/non-secure world partitioning of ETH, CAN, USB, and DMA - isolates firmware updates and cryptographic keys
Hardware DRAM encryption (AES-128)	On-the-fly encryption/decryption of DDR traffic - prevents cold-boot attacks without software overhead
Dual IEEE 1588v2 Ethernet MACs	Supports hardware timestamping, PTP transparent clock, and delay measurement - essential for TSN-compliant industrial automation
DFSDM + dual ADC	Simultaneous sigma-delta and SAR conversion - enables high-fidelity motor current sensing and vibration analysis
Secure boot with BSEC OTP	Immutable root-of-trust using SHA-256 signature verification and HUK-protected AES keys - blocks unauthorized firmware loading

Applications

Industrial HMI

Edge Gateway

Use Scenario: Touchscreen-based operator interface in PLC-controlled machinery with real-time diagnostics and remote firmware update capability.

IC Role / Device Role / Timing Role: Application processor running embedded Linux, managing GUI rendering, CAN FD fieldbus communication, and secure OTA updates via HTTPS + TLS.

Use Value: Dual Cortex-A7 delivers responsive UI performance while TrustZone isolates secure update logic; dual Ethernet enables redundant network connectivity with IEEE 1588 synchronization.

Use Scenario: Protocol translation hub aggregating Modbus RTU, CAN FD, and OPC UA over TLS for cloud telemetry in smart manufacturing.

IC Role / Device Role / Timing Role: Secure edge compute node executing protocol stacks, performing local analytics, and enforcing device identity via PKA-based certificate validation.

Use Value: Hardware-accelerated crypto (PKA, AES, SHA) offloads TLS handshake and signing; DFSDM+ADC enables analog sensor preprocessing before upload.

Secure IoT Node

Motor Control Gateway

Use Scenario: Tamper-resistant field device collecting environmental data and enforcing zero-trust access policies before transmitting encrypted payloads to AWS IoT Core.

IC Role / Device Role / Timing Role: Root-of-trust anchor with secure boot, runtime attestation, and hardware-enforced key storage using 256-bit HUK-protected AES keys.

Use Value: 12 tamper pins (5 active) detect physical intrusion; TRNG and HASH engines enable FIPS 140-2 Level 2 compliant key generation and integrity verification.

Use Scenario: Compact drive controller interfacing with BLDC motors via PWM, reading position sensors (Hall/encoder), and communicating status over CAN FD and Ethernet.

IC Role / Device Role / Timing Role: Real-time motion controller using quadrature encoder timers, DFSDM for current sensing, and dual CAN FD for actuator coordination.

Use Value: 2× 32-bit timers with quadrature input support precise rotor position tracking; dual ADCs sample phase currents at 5 Msps for field-oriented control loop closure.

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-core Arm Cortex-A7 microprocessor applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
STM32MP157C-DK2 (eval board)	Same MP1 family, but MP157C targets higher performance (1.5 GHz dual A7), larger L2 cache (256 KB), and adds GPU (Vivante GC7000Lite); lacks integrated DFSDM	Designed for graphics-rich HMI and multimedia; less optimized for sigma-delta sensor interfaces	Select when GUI rendering or video decode is required; avoid if DFSDM-based motor current sensing is critical
i.MX 8M Mini (NXP)	Quad-core Cortex-A53 + Cortex-M4, no TrustZone-peripheral isolation, different crypto IP (CAAM), no hardware DRAM encryption	Targets consumer media devices; weaker industrial security certification path (no BSEC OTP, fewer tamper pins)	Select for Android/Linux multimedia use cases; avoid where IEC 62443-3-3 SL2 compliance or tamper-evident design is mandatory

Compared with STM32MP133FAG7, the STM32MP157C offers higher CPU throughput but sacrifices DFSDM and tighter tamper integration, while i.MX 8M Mini provides broader OS support at the cost of hardware-enforced security granularity and deterministic Ethernet timing.

Availability

STM32MP133FAG7 is available at Aetrix Electronics and suitable for industrial HMIs, edge gateways, and secure IoT edge nodes requiring stable component supply, long-term lifecycle assurance, and qualified automotive-grade packaging.

Supply support for STM32MP133FAG7 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power ICs, sensors, and automotive-grade processors with ISO 9001 and IATF 16949 certification.

The STM32MP series targets Linux-capable edge computing with hardware-enforced security, targeting industrial automation, building control, and secure gateway applications where real-time responsiveness and certification readiness are mandatory.

FAQ

What boot sources does the STM32MP133FAG7 support?

The STM32MP133FAG7 supports five primary boot sources selected via BOOT0 and BOOT1 pins: Quad-SPI flash (QSPI), eMMC/SD card (SDMMC), parallel NOR/NAND (FSMC), USB device (DFU mode), and UART (for initial flashing). Boot sequence is managed by the ROM code, which verifies signed images using SHA-256 and RSA-2048 before loading into internal SRAM or DDR.

Does the STM32MP133FAG7 support hardware virtualization?

No - the STM32MP133FAG7 does not include a hardware virtualization extension (ARMv7-A Virtualization Extensions). It supports TrustZone-based secure/non-secure world separation and Linux kernel-based containerization, but lacks hypervisor-level instruction trapping or stage-2 MMU translation required for full Type 1 virtualization.

What is the maximum DDR bandwidth achievable with this processor?

The STM32MP133FAG7 DDR controller supports LPDDR3-1066 (1066 MT/s) or DDR3L-1066 in 16-bit configuration, delivering up to 2.1 GB/s peak theoretical bandwidth. Real-world sustained bandwidth depends on memory layout, AXI arbitration, and concurrent peripheral DMA usage - measured at ~1.6 GB/s in ST's reference design with dual Ethernet + USB active.

How is TrustZone implemented for peripheral access control?

TrustZone implementation uses the ETZPC (External TrustZone Protection Controller) and TZC (TrustZone Address Space Controller) to enforce access permissions. ETZPC gates peripheral clocks and resets based on secure state, while TZC filters AXI transactions to DDR, applying region-based read/write/execute permissions - verified at boot via BSEC-locked configuration registers and enforced in hardware without software intervention.

STM32MP133FAG7 Specifications

Product attributes: Attribute value

Manufacturer:: STMicroelectronics

Package/Case:: 289-TFBGA

Series:: STM32MP1

Packaging:: Tray

Product Status:: Active

Core Processor:: ARM® Cortex®-A7

Number of Cores/Bus Width:: 1 Core, 32-Bit

Speed:: 1GHz

Co-Processors/DSP:: Multimedia; NEON™ SIMD

RAM Controllers:: DDR3, DDR3L, LPDDR2, LPDDR3

Graphics Acceleration:: Yes

Display & Interface Controllers:: LCD

Ethernet:: 10/100/1000Mbps (2)

SATA:: -

USB:: USB 2.0 (2)

Voltage - I/O:: 1.8V, 2.5V, 3.3V

Operating Temperature:: -40°C ~ 105°C (TJ)

Grade:: -

Qualification:: -

Security Features:: AES, ARM TZ, Boot Security, Cryptography, Secure Debug, SHA-1/2, Tamper Detection, TRNG, Volatile key Storage

Mounting Type:: Surface Mount

Supplier Device Package:: 289-TFBGA (9x9)

Additional Interfaces:: CANbus, GPIO, I2C, I2S, IrDA, MMC/SD/SDIO, SAI, SPDIF, SPI, UART/USART

STM32MP133FAG7 FAQ

1.How can I place an order for STM32MP133FAG7 through Aetrix?

Please submit a Request for Quotation (RFQ) for STM32MP133FAG7 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for STM32MP133FAG7 reliable?

The price and inventory of STM32MP133FAG7 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for STM32MP133FAG7 is usually 5 days.

3.What payment methods are accepted for STM32MP133FAG7?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for STM32MP133FAG7 transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for STM32MP133FAG7?

STM32MP133FAG7 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your STM32MP133FAG7 order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for STM32MP133FAG7?

For technical support, including STM32MP133FAG7 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your STM32MP133FAG7 requirements.

6.How does Aetrix verify that STM32MP133FAG7 is sourced from the original manufacturer or authorized distributors?

All STM32MP133FAG7 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that STM32MP133FAG7 meets industry standards.

7.What is the process for return or replacement of STM32MP133FAG7?

All STM32MP133FAG7 units undergo pre-shipment inspection (PSI). If there is an issue with STM32MP133FAG7, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The STM32MP133FAG7 part is unused and in its original packaging.

Return procedure for STM32MP133FAG7:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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