STMicroelectronics STM32MP135AAF3

Overview

STM32MP135AAF3 from STMicroelectronics is a dual-core Arm® Cortex®-A7 microprocessor operating up to 1 GHz, integrating LCD-TFT controller (up to WXGA @60 fps), dual 12-bit ADCs (5 Msps), dual CAN FD controllers, dual Gigabit Ethernet MACs with IEEE 1588v2 hardware support, and TrustZone® security. It targets industrial HMI, edge gateway, and smart camera applications requiring real-time Linux-capable processing with integrated graphics and secure connectivity.

For engineers reviewing the STM32MP135AAF3 datasheet, STM32MP135AAF3 pinout, STM32MP135AAF3 application, or STM32MP135AAF3 equivalent, key selection considerations include DDR3/LPDDR3 memory interface timing, dual CAN FD protocol compliance, LCD-TFT pixel clock capability (up to 90 MHz), TrustZone-enabled peripheral isolation, and LFBGA289 (14 × 14 mm, 0.8 mm pitch) mechanical compatibility.

Technical Context

The STM32MP135AAF3 implements a heterogeneous dual-core Arm Cortex-A7 subsystem with 128 KB unified L2 cache, NEON™ SIMD acceleration, and TrustZone® for secure world/non-secure world partitioning. Its interconnect comprises a 64-bit AXI bus matrix (266 MHz) and 32-bit AHB matrix (209 MHz), enabling concurrent high-bandwidth access to DDR, SRAM, and peripherals.

It integrates two independent FDCAN controllers compliant with ISO 11898-1:2015 (CAN FD up to 5 Mbit/s), dual IEEE 802.3-compliant Ethernet MACs supporting MII/RMII/RGMII with hardware timestamping, and a dedicated DCMIPP camera pipe supporting 3 MPix @30 fps (color) at 120 MHz pixel clock - all accessible via deterministic DMA paths including MDMA and dual-port DMAs with request routing.

Key Specifications

Pinout & Package

LFBGA289 package (14 × 14 mm, 0.8 mm ball pitch, B0ED variant) with 289 I/O balls arranged in 17 × 17 array. Ball layout includes dedicated power/ground rings, DDR signal groups with controlled impedance routing, and isolated analog supply domains (VDDA, VREF+).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-core Arm Cortex-A7 microprocessor applications.

Compared with STM32MP135AAF3, the i.MX 8M Mini offers higher CPU throughput but requires external display controller and lacks hardware-enforced peripheral isolation - making STM32MP135AAF3 preferable for safety-certifiable HMI systems where display, CAN FD, and security must coexist on one die with minimal external components.

Availability

STM32MP135AAF3 is available at Aetrix Electronics and suitable for industrial HMI panels, edge gateways, and smart camera terminals requiring stable component supply, long-term lifecycle commitment, and ECOPACK2 environmental compliance.

Supply support for STM32MP135AAF3 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, specializing in microcontrollers, power management, sensors, and automotive ICs with strong industrial and automotive qualification heritage.

The STM32MP series targets Linux-capable embedded applications demanding real-time responsiveness, graphical UI, and hardware security - designed specifically for industrial automation, smart infrastructure, and medical edge devices where certification readiness and long-term supply stability are critical.

FAQ

What is the maximum supported DDR memory capacity and type for STM32MP135AAF3?

The STM32MP135AAF3 supports up to 1 Gbyte of external DDR memory using LPDDR2/LPDDR3-1066 (16-bit) or DDR3/DDR3L-1066 (16-bit). The DDR controller includes 8-bit ECC support for SLC NAND and implements hardware refresh management. Maximum bandwidth is constrained by 16-bit bus width and 1066 MT/s data rate, yielding ~2.1 GB/s theoretical peak throughput.

Does STM32MP135AAF3 include hardware support for IEEE 1588 Precision Time Protocol?

Yes - both Ethernet MACs (ETH1 and ETH2) integrate full IEEE 1588v2 hardware timestamping engines, supporting one-step and two-step clock synchronization, PTP event message filtering, and hardware-assisted correction of residence time and egress delay. Timestamp resolution is 1 ns with hardware compensation for PHY delays.

How many independent CAN FD interfaces does STM32MP135AAF3 provide, and what is their maximum bit rate?

The STM32MP135AAF3 integrates two fully independent FDCAN controllers (FDCAN1 and FDCAN2), each compliant with ISO 11898-1:2015. Both support CAN FD operation up to 5 Mbit/s in data phase with flexible bit-rate switching, payload lengths up to 64 bytes, and built-in message RAM with FIFO and TX queue management.

What package variant corresponds to the 'AAF3' suffix in STM32MP135AAF3?

The 'AAF3' suffix denotes the LFBGA289 package (14 × 14 mm, 0.8 mm ball pitch, B0ED marking), rated for industrial temperature range (–40 °C to +125 °C junction). This variant features enhanced thermal performance over TFBGA alternatives and is qualified for reflow soldering per J-STD-020D.3 standards.