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STMicroelectronics STM32MP135CAE3
- Part No.:
- STM32MP135CAE3
- Manufacturer:
- STMicroelectronics
- Category:
- Microprocessors
- Package:
- -
- Datasheet:
-
STM32MP135CAE3.pdf
- Description:
- 32-BIT ARM CORTEX-A7 650MHZ MPU
- Quantity:
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Inventory:135
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Product details
Overview
STM32MP135CAE3 from STMicroelectronics is a dual-core Arm® Cortex®-A7 microprocessor operating up to 1 GHz, integrating LCD-TFT controller, dual CAN FD interfaces, dual 12-bit ADCs (5 Msps), and hardware crypto accelerators (AES-256, PKA, HASH). It targets industrial HMI, edge gateway, and secure IoT gateway applications requiring real-time multimedia and advanced security.
For engineers reviewing the STM32MP135CAE3 datasheet, STM32MP135CAE3 pinout, STM32MP135CAE3 application, or STM32MP135CAE3 equivalent, key selection criteria include DDR3/LPDDR3 memory support, TrustZone®-enabled secure boot, dual Ethernet MAC with IEEE 1588v2, camera interface (3 Mpix @30 fps), and 135 secure GPIOs with tamper detection.
Technical Context
The STM32MP135CAE3 implements a heterogeneous dual-core Arm Cortex-A7 subsystem with 128 KB unified L2 cache, NEON™ SIMD, and TrustZone® for secure world/non-secure world isolation. It integrates dedicated security peripherals including BSEC OTP controller, ETZPC address space protection, and 12 tamper pins (5 active).
Its interconnect architecture features a 64-bit AXI bus matrix (266 MHz) and 32-bit AHB matrix (209 MHz), enabling concurrent high-bandwidth access to DDR, SRAM, and peripherals. The processor supports boot from Quad-SPI, NAND, SDMMC, or USB, with flexible clock tree driven by four fractional PLLs and multiple internal/external oscillators.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | Dual Arm Cortex-A7 @ up to 1 GHz with NEON and TrustZone |
| Memory Interface | 16-bit DDR3/LPDDR3-1066 support up to 1 Gbyte; 168 KB on-chip SRAM (128 KB AXI SYSRAM + 32 KB AHB SRAM + 8 KB backup) |
| Security | Secure boot, TrustZone peripherals, 12 tamper pins, AES-128/192/256 with DPA protection, PKA for ECC/RSA, on-the-fly DRAM encryption |
| Peripherals | 2× CAN FD, 2× Gigabit Ethernet (MII/RMII/RGMII), 2× USB 2.0 HS (Host/OTG), 8–16-bit camera interface (3 Mpix @30 fps), LCD-TFT controller (WXGA @60 fps) |
| Analog | 2× 12-bit ADCs (5 Msps), DFSDM with 4 channels, internal temperature sensor, VREFBUF |
| Timing & Debug | 24 timers (including advanced, general-purpose, low-power), secure RTC, Arm CoreSight trace with 4 KB ETB, SWD/JTAG debug |
Pinout & Package
LFBGA289 package (14 × 14 mm, 0.8 mm pitch), ECOPACK2-compliant, with 289 I/O balls arranged in 17 × 17 grid. Ball mapping includes dedicated power domains (VDDCORE, VDDCPU, VDDQ_DDR), DDR interface lanes (DQ[15:0], DQS, DM, CK, CKE, CS), and function-multiplexed I/Os supporting up to 135 secure GPIOs.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDDCORE | Core power supply | 1.0 V ±5% supply for CPU and logic; requires external PMIC regulation |
| VDDCPU | CPU voltage domain | Independent 0.8–1.1 V supply for Cortex-A7 cores; enables dynamic voltage scaling |
| VDDQ_DDR | DDR I/O supply | 1.2 V or 1.35 V supply for DDR3/LPDDR3 interface; matched to memory standard |
| NRST | Active-low reset input | Asynchronous system reset; monitored by embedded reset controller with glitch filtering |
| BOOT0 | Boot mode selection | Configures primary boot source (Quad-SPI/NAND/SDMMC/USB) at power-up |
Key Features
| Feature | Design Value |
|---|---|
| TrustZone-enabled secure execution | Hardware-enforced isolation between secure/non-secure worlds for firmware integrity and key protection |
| On-the-fly DRAM encryption | AES-128 engine encrypts/decrypts DDR traffic transparently without CPU overhead |
| Dual independent watchdogs (IWDG1/IWDG2) | Separate monitoring for secure and non-secure software stacks to prevent lockup escalation |
| Flexible camera interface (DCMIPP) | Supports 8–16-bit parallel sensors up to 120 MHz pixel clock; includes pipe processing for pre-processing |
| Hardware-accelerated crypto suite | CRYP (AES/DES/TDES), SAES (AES with DPA), PKA (ECC/RSA), HASH (SHA-256/512), RNG (3-oscillator TRNG) |
Applications
| Industrial HMI Panel | Secure Edge Gateway |
|---|---|
Use Scenario: Touch-enabled factory floor display with real-time process visualization and local control logic. IC Role / Device Role / Timing Role: Main application processor running Linux with QT-based UI; LCD-TFT controller drives 1366×768 panel at 60 fps; dual CAN FD interfaces communicate with PLCs and sensors. Use Value: Integrated graphics acceleration and 128 KB L2 cache reduce UI latency; TrustZone isolates HMI runtime from secure firmware updates. | Use Scenario: Field-deployable protocol translator aggregating Modbus, CAN FD, and Ethernet data for cloud upload. IC Role / Device Role / Timing Role: Dual-core A7 executes real-time protocol stacks (CAN FD, EtherCAT) on secure world and Linux application on non-secure world; dual Ethernet MACs handle upstream/downstream traffic with IEEE 1588v2 time sync. Use Value: Hardware crypto accelerators enable TLS 1.3 offload; on-the-fly DRAM encryption protects cached telemetry before transmission. |
| Smart Building Controller | Medical Imaging Edge Node |
Use Scenario: HVAC and lighting controller with local analytics, touchscreen UI, and secure remote diagnostics. IC Role / Device Role / Timing Role: Runs Yocto Linux with containerized services; 2× USB 2.0 HS ports connect to diagnostic dongle and peripheral HID devices; 135 GPIOs interface with relays, temp sensors, and tamper switches. Use Value: 12 tamper pins detect physical intrusion attempts; secure RTC with sub-second accuracy timestamps audit logs independently of network time. | Use Scenario: Portable ultrasound or endoscopy device capturing and preprocessing raw image data before compression and transmission. IC Role / Device Role / Timing Role: Camera interface ingests 3 Mpix @30 fps monochrome video; DFSDM processes sigma-delta audio feedback; SAI/SPDIF handles synchronized audio output. Use Value: Dedicated DCMIPP pipeline reduces CPU load for real-time image buffering; 5 Msps ADCs digitize analog sensor signals with minimal jitter. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-core Arm Cortex-A7 microprocessor applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| STM32MP157C-DK2 | Same core, but higher-performance variant with dual Cortex-A7 @ 800 MHz and single Cortex-M4 coprocessor; supports LPDDR4 and PCIe | Targeted at more demanding edge AI inference and multi-camera systems where M4 offloads real-time control | Select when needing M4 co-processor for deterministic real-time tasks alongside Linux application layer |
| i.MX 8M Mini (NXP) | Quad Cortex-A53 + Cortex-M4; lacks TrustZone-peripheral granularity and integrated DRAM encryption; different security IP (CAAM vs. ST BSEC) | Better suited for Android-based multimedia gateways; weaker hardware root-of-trust implementation for certified secure boot | Choose for Android compatibility or when A53 performance > A7 efficiency is required, accepting trade-offs in security hardening |
Compared with STM32MP135CAE3, the STM32MP157C-DK2 adds an M4 coprocessor and LPDDR4 support for enhanced real-time capability, while the i.MX 8M Mini offers quad-A53 throughput at the cost of finer-grained TrustZone peripheral control and on-the-fly DRAM encryption.
Availability
STM32MP135CAE3 is available at Aetrix Electronics and suitable for industrial HMI, secure edge gateways, smart building controllers, and medical imaging edge nodes requiring stable component supply across long-lifecycle deployments.
Supply support for STM32MP135CAE3 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, specializing in microcontrollers, power management, sensors, and automotive ICs with strong focus on industrial and embedded markets.
The STM32MP series is designed specifically for Linux-capable, resource-constrained edge applications requiring hardware-enforced security, real-time responsiveness, and rich peripheral integration - bridging the gap between MCUs and application processors.
FAQ
What boot sources does the STM32MP135CAE3 support?
The STM32MP135CAE3 supports boot from Quad-SPI flash, SLC NAND, SD/eMMC, USB mass storage, and UART via serial loader. Boot mode is selected using BOOT0 and BOOT1 pins, with fallback to internal ROM bootloader if no valid image is found. Each source has configurable partitioning and authentication options via BSEC fuses.
Does the STM32MP135CAE3 include a built-in PMIC?
No, the STM32MP135CAE3 does not integrate a PMIC. It relies on external power management ICs to generate its multiple voltage domains: VDDCORE (1.0 V), VDDCPU (0.8–1.1 V), VDDIO (1.8/3.3 V), and VDDQ_DDR (1.2/1.35 V). The chip provides PMIC control signals (e.g., PWRCTRL, VSEL) and monitors rail status via internal sensors.
How many DDR memory channels does the STM32MP135CAE3 support?
The STM32MP135CAE3 supports a single 16-bit DDR channel for LPDDR2/LPDDR3 or DDR3/DDR3L memory, with maximum bandwidth of 1066 MT/s. It does not support dual-channel or 32-bit DDR interfaces. Memory capacity is limited to 1 Gbyte, and the controller includes 8-bit ECC for SLC NAND interfacing via FMC.
Can the STM32MP135CAE3 run bare-metal code on the Cortex-A7 cores?
Yes, the Cortex-A7 cores can execute bare-metal code, but ST recommends using the Arm Trusted Firmware (ATF) and OP-TEE secure OS stack to leverage TrustZone, secure boot, and peripheral protection. Bare-metal use bypasses hardware security features and requires manual configuration of MMU, caches, and interrupt controllers - not supported in official ST SDKs.
STM32MP135CAE3 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Package/Case:
- -
- Series:
- -
- Packaging:
- Tray
- Product Status:
- Active
- Core Processor:
- -
- Number of Cores/Bus Width:
- -
- Speed:
- -
- Co-Processors/DSP:
- -
- RAM Controllers:
- -
- Graphics Acceleration:
- -
- Display & Interface Controllers:
- -
- Ethernet:
- -
- SATA:
- -
- USB:
- -
- Voltage - I/O:
- -
- Operating Temperature:
- -
- Grade:
- -
- Qualification:
- -
- Security Features:
- -
- Mounting Type:
- -
- Supplier Device Package:
- -
- Additional Interfaces:
- -
STM32MP135CAE3 FAQ
1.How can I place an order for STM32MP135CAE3 through Aetrix?
Please submit a Request for Quotation (RFQ) for STM32MP135CAE3 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for STM32MP135CAE3 reliable?
The price and inventory of STM32MP135CAE3 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for STM32MP135CAE3 is usually 5 days.
3.What payment methods are accepted for STM32MP135CAE3?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for STM32MP135CAE3 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for STM32MP135CAE3?
STM32MP135CAE3 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your STM32MP135CAE3 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for STM32MP135CAE3?
For technical support, including STM32MP135CAE3 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your STM32MP135CAE3 requirements.
6.How does Aetrix verify that STM32MP135CAE3 is sourced from the original manufacturer or authorized distributors?
All STM32MP135CAE3 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that STM32MP135CAE3 meets industry standards.
7.What is the process for return or replacement of STM32MP135CAE3?
All STM32MP135CAE3 units undergo pre-shipment inspection (PSI). If there is an issue with STM32MP135CAE3, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The STM32MP135CAE3 part is unused and in its original packaging.
Return procedure for STM32MP135CAE3:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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