STMicroelectronics STM32MP135CAF3

Overview

STM32MP135CAF3 from STMicroelectronics is a dual-core Arm® Cortex®-A7 microprocessor operating up to 1 GHz, featuring TrustZone® security, dual 10/100/1000 Mbps Ethernet MACs, two CAN FD controllers, LCD-TFT display controller supporting Full HD @30 fps, and hardware-accelerated AES-256/SHA-512 crypto. It integrates 128 KB L2 cache, 168 KB on-chip SRAM (128 KB AXI SYSRAM + 32 KB AHB SRAM + 8 KB backup SRAM), and supports LPDDR3-1066/DDR3L-1066 external memory for industrial HMI and edge gateway applications.

For engineers reviewing the STM32MP135CAF3 datasheet, STM32MP135CAF3 pinout, STM32MP135CAF3 application, or STM32MP135CAF3 equivalent, key selection criteria include dual-Cortex-A7 performance with TrustZone isolation, 2×CAN FD + 2×Gigabit Ethernet for deterministic industrial networking, LCD-TFT + camera interface for vision-enabled HMIs, and on-die crypto accelerators meeting IEC 62443-3-3 SL2 requirements.

Technical Context

The STM32MP135CAF3 implements a heterogeneous dual-core Arm Cortex-A7 subsystem with shared 128 KB unified L2 cache, NEON SIMD extensions, and full TrustZone address space partitioning across peripherals and DDR via TZC. Its interconnect uses a 64-bit AXI bus matrix (266 MHz) and 32-bit AHB matrix (209 MHz) to coordinate CPU, DMA, and peripheral traffic.

Security architecture includes secure boot enforced by BSEC OTP fuses, 12 tamper pins (5 active), TrustZone-peripheral protection (ETZPC), on-the-fly AES-256 DRAM encryption, and PKA/ECC acceleration with DPA resistance. Power management supports five low-power modes including Standby with DDR retention and LPLV-Stop2 with sub-10 µA core leakage.

Key Specifications

Pinout & Package

STM32MP135CAF3 is housed in a TFBGA289 package (9 × 9 mm, 0.5 mm ball pitch), with 289 I/O balls arranged in a 17×17 grid excluding corner blanks. The package supports 135 secure GPIOs with interrupt/wakeup capability, 5 V-tolerant I/Os, and dedicated power/ground ball patterns optimized for DDR signal integrity and thermal dissipation.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-core application processor applications.

Compared with i.MX 8M Mini and RZ/G2L, STM32MP135CAF3 uniquely combines dual Cortex-A7 with industrial-grade security (12 tamper pins, BSEC OTP), dual CAN FD + dual Gigabit Ethernet with IEEE 1588v2, and on-die DRAM encryption-making it the only option qualified for IEC 62443-3-3 SL2-compliant edge gateways requiring deterministic fieldbus convergence.

Availability

STM32MP135CAF3 is available at Aetrix Electronics and suitable for industrial HMI terminals, edge protocol gateways, smart building video entry systems, and medical imaging edge nodes requiring stable component supply across 10+ year product lifecycles.

Supply support for STM32MP135CAF3 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power ICs, sensors, and automotive semiconductors with vertical fabrication capacity.

The STM32MP series targets Linux-capable edge devices requiring real-time responsiveness, hardware security, and industrial connectivity-designed specifically for HMI, gateway, and vision-enabled embedded applications where MPU performance meets MCU-level robustness.

FAQ

What boot sources does the STM32MP135CAF3 support?

The STM32MP135CAF3 supports boot from Quad-SPI flash, parallel NOR/NAND (via FMC), SD/eMMC, USB device, and serial interfaces (UART, I2C, SPI) using BOOT0/BOOT1 strapping. Boot mode selection is latched at power-on reset and validated by the ROM code before loading FSBL from the selected medium.

Does the STM32MP135CAF3 include hardware debug support?

Yes-it integrates Arm CoreSight™ infrastructure with SWD and JTAG interfaces usable as GPIOs after configuration, plus a 4 KB embedded trace buffer for instruction and data trace. Debug authentication is enforced via TrustZone, restricting access to secure world debug sessions unless explicitly authorized.

How is DDR memory retention managed during low-power modes?

In Standby mode, the STM32MP135CAF3 maintains DDR self-refresh with VDDQ_DDR powered, preserving full DRAM contents while CPU and most peripherals are powered down. This enables sub-100 ms wake-up to full operation with no memory reload, critical for maintaining network session state and real-time control context.

What is the maximum camera resolution and frame rate supported?

The STM32MP135CAF3's DCMIPP interface supports up to 5 MP resolution at 15 fps in color or monochrome mode, with pixel clock up to 120 MHz. At lower resolutions like 3 MP, it achieves 30 fps-enabling real-time video analytics on Arm NEON without external FPGA offload.